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jyknightjyknight
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[X86] Rearrange a few atomics tests. NFC.
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6 files changed

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-928
lines changed

6 files changed

+407
-928
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‎llvm/test/CodeGen/X86/atomic-nocx16.ll

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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; RUN: llc < %s -mtriple=x86_64-- -verify-machineinstrs -mcpu=corei7 -mattr=-cx16 | FileCheck %s
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; RUN: llc < %s -mtriple=i386-linux-gnu -verify-machineinstrs -mattr=cx16 | FileCheck -check-prefix=CHECK %s
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;; Verify that 128-bit atomics emit a libcall without cx16
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;; available.
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;;
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;; We test 32-bit mode with -mattr=cx16, because it should have no
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;; effect for 32-bit mode.
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; CHECK-LABEL: test:
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define void @test(ptr %a) nounwind {
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entry:
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; CHECK: __sync_val_compare_and_swap_16
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%0 = cmpxchg ptr %a, i128 1, i128 1 seq_cst seq_cst
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; CHECK: __sync_lock_test_and_set_16
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%1 = atomicrmw xchg ptr %a, i128 1 seq_cst
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; CHECK: __sync_fetch_and_add_16
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%2 = atomicrmw add ptr %a, i128 1 seq_cst
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; CHECK: __sync_fetch_and_sub_16
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%3 = atomicrmw sub ptr %a, i128 1 seq_cst
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; CHECK: __sync_fetch_and_and_16
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%4 = atomicrmw and ptr %a, i128 1 seq_cst
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; CHECK: __sync_fetch_and_nand_16
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%5 = atomicrmw nand ptr %a, i128 1 seq_cst
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; CHECK: __sync_fetch_and_or_16
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%6 = atomicrmw or ptr %a, i128 1 seq_cst
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; CHECK: __sync_fetch_and_xor_16
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%7 = atomicrmw xor ptr %a, i128 1 seq_cst
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; CHECK: __sync_val_compare_and_swap_16
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%8 = load atomic i128, ptr %a seq_cst, align 16
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; CHECK: __sync_lock_test_and_set_16
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store atomic i128 %8, ptr %a seq_cst, align 16
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ret void
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}
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; CHECK-LABEL: test_fp:
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define void @test_fp(fp128* %a) nounwind {
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entry:
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; CHECK: __sync_lock_test_and_set_16
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%0 = atomicrmw xchg fp128* %a, fp128 0xL00000000000000004000900000000000 seq_cst
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; Currently fails to compile:
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; %1 = atomicrmw fadd fp128* %a, fp128 0xL00000000000000004000900000000000 seq_cst
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; %2 = atomicrmw fsub fp128* %a, fp128 0xL00000000000000004000900000000000 seq_cst
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; CHECK: __sync_val_compare_and_swap_16
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%1 = load atomic fp128, fp128* %a seq_cst, align 16
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; CHECK: __sync_lock_test_and_set_16
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store atomic fp128 %1, fp128* %a seq_cst, align 16
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ret void
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}

‎llvm/test/CodeGen/X86/atomic-non-integer-fp128.ll

Lines changed: 128 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1,35 +1,139 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=x86_64-linux-generic -verify-machineinstrs -mattr=-sse | FileCheck %s --check-prefix=X64-NOSSE
3-
; RUN: llc < %s -mtriple=x86_64-linux-generic -verify-machineinstrs | FileCheck %s --check-prefix=X64-SSE
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; RUN: llc < %s -mtriple=x86_64-linux-generic -verify-machineinstrs -mattr=sse2,cx16 | FileCheck %s --check-prefixes=X64-SSE
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; RUN: llc < %s -mtriple=x86_64-linux-generic -verify-machineinstrs -mattr=avx,cx16 | FileCheck %s --check-prefixes=X64-AVX
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; RUN: llc < %s -mtriple=x86_64-linux-generic -verify-machineinstrs -mattr=avx512f,cx16 | FileCheck %s --check-prefixes=X64-AVX
45

5-
; Note: This test is testing that the lowering for atomics matches what we
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; currently emit for non-atomics + the atomic restriction. The presence of
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; particular lowering detail in these tests should not be read as requiring
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; that detail for correctness unless it's related to the atomicity itself.
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; (Specifically, there were reviewer questions about the lowering for halfs
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; and their calling convention which remain unresolved.)
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; Codegen of fp128 without cx16 is tested in atomic-nocx16.ll
117

128
define void @store_fp128(ptr %fptr, fp128 %v) {
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; X64-NOSSE-LABEL: store_fp128:
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; X64-NOSSE: # %bb.0:
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; X64-NOSSE-NEXT: pushq %rax
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; X64-NOSSE-NEXT: .cfi_def_cfa_offset 16
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; X64-NOSSE-NEXT: callq __sync_lock_test_and_set_16@PLT
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; X64-NOSSE-NEXT: popq %rax
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; X64-NOSSE-NEXT: .cfi_def_cfa_offset 8
20-
; X64-NOSSE-NEXT: retq
21-
;
229
; X64-SSE-LABEL: store_fp128:
2310
; X64-SSE: # %bb.0:
24-
; X64-SSE-NEXT: subq $24, %rsp
25-
; X64-SSE-NEXT: .cfi_def_cfa_offset 32
26-
; X64-SSE-NEXT: movaps %xmm0, (%rsp)
27-
; X64-SSE-NEXT: movq (%rsp), %rsi
28-
; X64-SSE-NEXT: movq {{[0-9]+}}(%rsp), %rdx
29-
; X64-SSE-NEXT: callq __sync_lock_test_and_set_16@PLT
30-
; X64-SSE-NEXT: addq $24, %rsp
11+
; X64-SSE-NEXT: pushq %rbx
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; X64-SSE-NEXT: .cfi_def_cfa_offset 16
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; X64-SSE-NEXT: .cfi_offset %rbx, -16
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; X64-SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
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; X64-SSE-NEXT: movq -{{[0-9]+}}(%rsp), %rbx
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; X64-SSE-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
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; X64-SSE-NEXT: movq (%rdi), %rax
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; X64-SSE-NEXT: movq 8(%rdi), %rdx
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; X64-SSE-NEXT: .p2align 4, 0x90
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; X64-SSE-NEXT: .LBB0_1: # %atomicrmw.start
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; X64-SSE-NEXT: # =>This Inner Loop Header: Depth=1
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; X64-SSE-NEXT: lock cmpxchg16b (%rdi)
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; X64-SSE-NEXT: jne .LBB0_1
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; X64-SSE-NEXT: # %bb.2: # %atomicrmw.end
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; X64-SSE-NEXT: popq %rbx
3126
; X64-SSE-NEXT: .cfi_def_cfa_offset 8
3227
; X64-SSE-NEXT: retq
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;
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; X64-AVX-LABEL: store_fp128:
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; X64-AVX: # %bb.0:
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; X64-AVX-NEXT: pushq %rbx
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; X64-AVX-NEXT: .cfi_def_cfa_offset 16
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; X64-AVX-NEXT: .cfi_offset %rbx, -16
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; X64-AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
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; X64-AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rbx
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; X64-AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
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; X64-AVX-NEXT: movq (%rdi), %rax
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; X64-AVX-NEXT: movq 8(%rdi), %rdx
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; X64-AVX-NEXT: .p2align 4, 0x90
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; X64-AVX-NEXT: .LBB0_1: # %atomicrmw.start
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; X64-AVX-NEXT: # =>This Inner Loop Header: Depth=1
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; X64-AVX-NEXT: lock cmpxchg16b (%rdi)
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; X64-AVX-NEXT: jne .LBB0_1
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; X64-AVX-NEXT: # %bb.2: # %atomicrmw.end
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; X64-AVX-NEXT: popq %rbx
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; X64-AVX-NEXT: .cfi_def_cfa_offset 8
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; X64-AVX-NEXT: retq
3348
store atomic fp128 %v, ptr %fptr unordered, align 16
3449
ret void
3550
}
51+
52+
define fp128 @load_fp128(ptr %fptr) {
53+
; X64-SSE-LABEL: load_fp128:
54+
; X64-SSE: # %bb.0:
55+
; X64-SSE-NEXT: pushq %rbx
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; X64-SSE-NEXT: .cfi_def_cfa_offset 16
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; X64-SSE-NEXT: .cfi_offset %rbx, -16
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; X64-SSE-NEXT: xorl %eax, %eax
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; X64-SSE-NEXT: xorl %edx, %edx
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; X64-SSE-NEXT: xorl %ecx, %ecx
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; X64-SSE-NEXT: xorl %ebx, %ebx
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; X64-SSE-NEXT: lock cmpxchg16b (%rdi)
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; X64-SSE-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
64+
; X64-SSE-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
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; X64-SSE-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0
66+
; X64-SSE-NEXT: popq %rbx
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; X64-SSE-NEXT: .cfi_def_cfa_offset 8
68+
; X64-SSE-NEXT: retq
69+
;
70+
; X64-AVX-LABEL: load_fp128:
71+
; X64-AVX: # %bb.0:
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; X64-AVX-NEXT: pushq %rbx
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; X64-AVX-NEXT: .cfi_def_cfa_offset 16
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; X64-AVX-NEXT: .cfi_offset %rbx, -16
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; X64-AVX-NEXT: xorl %eax, %eax
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; X64-AVX-NEXT: xorl %edx, %edx
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; X64-AVX-NEXT: xorl %ecx, %ecx
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; X64-AVX-NEXT: xorl %ebx, %ebx
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; X64-AVX-NEXT: lock cmpxchg16b (%rdi)
80+
; X64-AVX-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
81+
; X64-AVX-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
82+
; X64-AVX-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0
83+
; X64-AVX-NEXT: popq %rbx
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; X64-AVX-NEXT: .cfi_def_cfa_offset 8
85+
; X64-AVX-NEXT: retq
86+
%v = load atomic fp128, ptr %fptr unordered, align 16
87+
ret fp128 %v
88+
}
89+
90+
define fp128 @exchange_fp128(ptr %fptr, fp128 %x) {
91+
; X64-SSE-LABEL: exchange_fp128:
92+
; X64-SSE: # %bb.0:
93+
; X64-SSE-NEXT: pushq %rbx
94+
; X64-SSE-NEXT: .cfi_def_cfa_offset 16
95+
; X64-SSE-NEXT: .cfi_offset %rbx, -16
96+
; X64-SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
97+
; X64-SSE-NEXT: movq -{{[0-9]+}}(%rsp), %rbx
98+
; X64-SSE-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
99+
; X64-SSE-NEXT: movq (%rdi), %rax
100+
; X64-SSE-NEXT: movq 8(%rdi), %rdx
101+
; X64-SSE-NEXT: .p2align 4, 0x90
102+
; X64-SSE-NEXT: .LBB2_1: # %atomicrmw.start
103+
; X64-SSE-NEXT: # =>This Inner Loop Header: Depth=1
104+
; X64-SSE-NEXT: lock cmpxchg16b (%rdi)
105+
; X64-SSE-NEXT: jne .LBB2_1
106+
; X64-SSE-NEXT: # %bb.2: # %atomicrmw.end
107+
; X64-SSE-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
108+
; X64-SSE-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
109+
; X64-SSE-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0
110+
; X64-SSE-NEXT: popq %rbx
111+
; X64-SSE-NEXT: .cfi_def_cfa_offset 8
112+
; X64-SSE-NEXT: retq
113+
;
114+
; X64-AVX-LABEL: exchange_fp128:
115+
; X64-AVX: # %bb.0:
116+
; X64-AVX-NEXT: pushq %rbx
117+
; X64-AVX-NEXT: .cfi_def_cfa_offset 16
118+
; X64-AVX-NEXT: .cfi_offset %rbx, -16
119+
; X64-AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
120+
; X64-AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rbx
121+
; X64-AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
122+
; X64-AVX-NEXT: movq (%rdi), %rax
123+
; X64-AVX-NEXT: movq 8(%rdi), %rdx
124+
; X64-AVX-NEXT: .p2align 4, 0x90
125+
; X64-AVX-NEXT: .LBB2_1: # %atomicrmw.start
126+
; X64-AVX-NEXT: # =>This Inner Loop Header: Depth=1
127+
; X64-AVX-NEXT: lock cmpxchg16b (%rdi)
128+
; X64-AVX-NEXT: jne .LBB2_1
129+
; X64-AVX-NEXT: # %bb.2: # %atomicrmw.end
130+
; X64-AVX-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
131+
; X64-AVX-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
132+
; X64-AVX-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0
133+
; X64-AVX-NEXT: popq %rbx
134+
; X64-AVX-NEXT: .cfi_def_cfa_offset 8
135+
; X64-AVX-NEXT: retq
136+
%v = atomicrmw xchg ptr %fptr, fp128 %x monotonic, align 16
137+
ret fp128 %v
138+
}
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