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[AArch64] Add support for Cortex-A725 and Cortex-X925 (#95214)
Cortex-A725 and Cortex-X925 are Armv9.2 AArch64 CPUs. Technical Reference Manual for Cortex-A725: https://developer.arm.com/documentation/107652/latest Technical Reference Manual for Cortex-X925: https://developer.arm.com/documentation/102807/latest
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‎clang/docs/ReleaseNotes.rst

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -903,11 +903,13 @@ Arm and AArch64 Support
903903
a feature modifier for -march and -mcpu as well as via target attributes
904904
like ``target_version`` or ``target_clones``.
905905
- Support has been added for the following processors (-mcpu identifiers in parenthesis):
906+
* Arm Cortex-R52+ (cortex-r52plus).
907+
* Arm Cortex-R82AE (cortex-r82ae).
906908
* Arm Cortex-A78AE (cortex-a78ae).
907909
* Arm Cortex-A520AE (cortex-a520ae).
908910
* Arm Cortex-A720AE (cortex-a720ae).
909-
* Arm Cortex-R82AE (cortex-r82ae).
910-
* Arm Cortex-R52+ (cortex-r52plus).
911+
* Arm Cortex-A725 (cortex-a725).
912+
* Arm Cortex-X925 (cortex-x925).
911913
* Arm Neoverse-N3 (neoverse-n3).
912914
* Arm Neoverse-V3 (neoverse-v3).
913915
* Arm Neoverse-V3AE (neoverse-v3ae).

‎clang/test/Driver/aarch64-mcpu.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,8 @@
4646
// CORTEXX3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x3"
4747
// RUN: %clang --target=aarch64 -mcpu=cortex-x4 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-X4 %s
4848
// CORTEX-X4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x4"
49+
// RUN: %clang --target=aarch64 -mcpu=cortex-x925 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-X925 %s
50+
// CORTEX-X925: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x925"
4951
// RUN: %clang --target=aarch64 -mcpu=cortex-a78 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEXA78 %s
5052
// CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
5153
// RUN: %clang --target=aarch64 -mcpu=cortex-a78c -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A78C %s
@@ -58,6 +60,8 @@
5860
// CORTEX-A720: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a720"
5961
// RUN: %clang --target=aarch64 -mcpu=cortex-a720ae -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A720AE %s
6062
// CORTEX-A720AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a720ae"
63+
// RUN: %clang --target=aarch64 -mcpu=cortex-a725 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A725 %s
64+
// CORTEX-A725: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a725"
6165
// RUN: %clang --target=aarch64 -mcpu=neoverse-e1 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-E1 %s
6266
// NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-e1"
6367
// RUN: %clang --target=aarch64 -mcpu=neoverse-v1 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-V1 %s

‎clang/test/Misc/target-invalid-cpu-note.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,11 @@
55

66
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64
77
// AARCH64: error: unknown target CPU 'not-a-cpu'
8-
// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, oryon-1, cobalt-100, grace{{$}}
8+
// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-a725, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, cortex-x925, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, oryon-1, cobalt-100, grace{{$}}
99

1010
// RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
1111
// TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
12-
// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, oryon-1, cobalt-100, grace{{$}}
12+
// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-a725, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, cortex-x925, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, oryon-1, cobalt-100, grace{{$}}
1313

1414
// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
1515
// X86: error: unknown target CPU 'not-a-cpu'

‎llvm/docs/ReleaseNotes.rst

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -92,8 +92,8 @@ Changes to Interprocedural Optimizations
9292
Changes to the AArch64 Backend
9393
------------------------------
9494

95-
* Added support for Cortex-A78AE, Cortex-A520AE, Cortex-A720AE,
96-
Cortex-R82AE, Neoverse-N3, Neoverse-V3 and Neoverse-V3AE CPUs.
95+
* Added support for Cortex-R82AE, Cortex-A78AE, Cortex-A520AE, Cortex-A720AE,
96+
Cortex-A725, Cortex-X925, Neoverse-N3, Neoverse-V3 and Neoverse-V3AE CPUs.
9797

9898
* ``-mbranch-protection=standard`` now enables FEAT_PAuth_LR by
9999
default when the feature is enabled. The new behaviour results

‎llvm/include/llvm/TargetParser/AArch64TargetParser.h

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Original file line numberDiff line numberDiff line change
@@ -322,6 +322,12 @@ inline constexpr CpuInfo CpuInfos[] = {
322322
AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
323323
AArch64::AEK_FLAGM, AArch64::AEK_PERFMON,
324324
AArch64::AEK_PREDRES, AArch64::AEK_PROFILE})},
325+
{"cortex-a725", ARMV9_2A,
326+
AArch64::ExtensionBitset(
327+
{AArch64::AEK_MTE, AArch64::AEK_SSBS, AArch64::AEK_SB,
328+
AArch64::AEK_PREDRES, AArch64::AEK_FP16FML, AArch64::AEK_PAUTH,
329+
AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_SVE2BITPERM,
330+
AArch64::AEK_PROFILE})},
325331
{"cortex-r82", ARMV8R,
326332
AArch64::ExtensionBitset({AArch64::AEK_LSE, AArch64::AEK_FLAGM,
327333
AArch64::AEK_PERFMON, AArch64::AEK_PREDRES})},
@@ -357,6 +363,12 @@ inline constexpr CpuInfo CpuInfos[] = {
357363
AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
358364
AArch64::AEK_FLAGM, AArch64::AEK_PERFMON,
359365
AArch64::AEK_PREDRES, AArch64::AEK_PROFILE})},
366+
{"cortex-x925", ARMV9_2A,
367+
AArch64::ExtensionBitset({AArch64::AEK_SB, AArch64::AEK_SSBS,
368+
AArch64::AEK_MTE, AArch64::AEK_FP16FML,
369+
AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
370+
AArch64::AEK_SVE2BITPERM, AArch64::AEK_PERFMON,
371+
AArch64::AEK_PREDRES, AArch64::AEK_PROFILE})},
360372
{"neoverse-e1", ARMV8_2A,
361373
AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,
362374
AArch64::AEK_DOTPROD, AArch64::AEK_FP16,

‎llvm/lib/Target/AArch64/AArch64Processors.td

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -189,6 +189,17 @@ def TuneA720AE : SubtargetFeature<"a720ae", "ARMProcFamily", "CortexA720",
189189
FeatureEnableSelectOptimize,
190190
FeaturePredictableSelectIsExpensive]>;
191191

192+
def TuneA725 : SubtargetFeature<"cortex-a725", "ARMProcFamily",
193+
"CortexA725",
194+
"Cortex-A725 ARM processors", [
195+
FeatureFuseAES,
196+
FeaturePostRAScheduler,
197+
FeatureCmpBccFusion,
198+
FeatureALULSLFast,
199+
FeatureFuseAdrpAdd,
200+
FeatureEnableSelectOptimize,
201+
FeaturePredictableSelectIsExpensive]>;
202+
192203
def TuneR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily",
193204
"CortexR82",
194205
"Cortex-R82 ARM processors", [
@@ -238,6 +249,15 @@ def TuneX4 : SubtargetFeature<"cortex-x4", "ARMProcFamily", "CortexX4",
238249
FeatureEnableSelectOptimize,
239250
FeaturePredictableSelectIsExpensive]>;
240251

252+
def TuneX925 : SubtargetFeature<"cortex-x925", "ARMProcFamily",
253+
"CortexX925", "Cortex-X925 ARM processors",[
254+
FeatureALULSLFast,
255+
FeatureFuseAdrpAdd,
256+
FeatureFuseAES,
257+
FeaturePostRAScheduler,
258+
FeatureEnableSelectOptimize,
259+
FeaturePredictableSelectIsExpensive]>;
260+
241261
def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX",
242262
"Fujitsu A64FX processors", [
243263
FeaturePostRAScheduler,
@@ -691,6 +711,9 @@ def ProcessorFeatures {
691711
list<SubtargetFeature> A720AE = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
692712
FeatureTRBE, FeatureSVE2BitPerm, FeatureETE,
693713
FeaturePerfMon, FeatureSPE, FeatureSPE_EEF];
714+
list<SubtargetFeature> A725 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
715+
FeatureETE, FeaturePerfMon, FeatureSPE,
716+
FeatureSVE2BitPerm, FeatureSPE_EEF, FeatureTRBE];
694717
list<SubtargetFeature> R82 = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16,
695718
FeatureFP16FML, FeatureSSBS, FeaturePredRes,
696719
FeatureSB, FeatureRDM, FeatureDotProd,
@@ -723,6 +746,9 @@ def ProcessorFeatures {
723746
FeaturePerfMon, FeatureETE, FeatureTRBE,
724747
FeatureSPE, FeatureMTE, FeatureSVE2BitPerm,
725748
FeatureFP16FML, FeatureSPE_EEF];
749+
list<SubtargetFeature> X925 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
750+
FeatureETE, FeaturePerfMon, FeatureSPE,
751+
FeatureSVE2BitPerm, FeatureSPE_EEF, FeatureTRBE];
726752
list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON,
727753
FeatureSHA2, FeaturePerfMon, FeatureFullFP16,
728754
FeatureSVE, FeatureComplxNum];
@@ -891,6 +917,8 @@ def : ProcessorModel<"cortex-a720", NeoverseN2Model, ProcessorFeatures.A720,
891917
[TuneA720]>;
892918
def : ProcessorModel<"cortex-a720ae", NeoverseN2Model, ProcessorFeatures.A720AE,
893919
[TuneA720AE]>;
920+
def : ProcessorModel<"cortex-a725", NeoverseN2Model, ProcessorFeatures.A725,
921+
[TuneA725]>;
894922
def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82,
895923
[TuneR82]>;
896924
def : ProcessorModel<"cortex-r82ae", CortexA55Model, ProcessorFeatures.R82AE,
@@ -905,6 +933,8 @@ def : ProcessorModel<"cortex-x3", NeoverseN2Model, ProcessorFeatures.X3,
905933
[TuneX3]>;
906934
def : ProcessorModel<"cortex-x4", NeoverseN2Model, ProcessorFeatures.X4,
907935
[TuneX4]>;
936+
def : ProcessorModel<"cortex-x925", NeoverseV2Model, ProcessorFeatures.X925,
937+
[TuneX925]>;
908938
def : ProcessorModel<"neoverse-e1", CortexA53Model,
909939
ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>;
910940
def : ProcessorModel<"neoverse-n1", NeoverseN1Model,

‎llvm/lib/Target/AArch64/AArch64Subtarget.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -153,9 +153,11 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
153153
case CortexA710:
154154
case CortexA715:
155155
case CortexA720:
156+
case CortexA725:
156157
case CortexX2:
157158
case CortexX3:
158159
case CortexX4:
160+
case CortexX925:
159161
PrefFunctionAlignment = Align(16);
160162
VScaleForTuning = 1;
161163
PrefLoopAlignment = Align(32);

‎llvm/lib/TargetParser/Host.cpp

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Original file line numberDiff line numberDiff line change
@@ -239,11 +239,13 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
239239
.Case("0xd4d", "cortex-a715")
240240
.Case("0xd81", "cortex-a720")
241241
.Case("0xd89", "cortex-a720ae")
242+
.Case("0xd87", "cortex-a725")
242243
.Case("0xd44", "cortex-x1")
243244
.Case("0xd4c", "cortex-x1c")
244245
.Case("0xd48", "cortex-x2")
245246
.Case("0xd4e", "cortex-x3")
246247
.Case("0xd82", "cortex-x4")
248+
.Case("0xd85", "cortex-x925")
247249
.Case("0xd4a", "neoverse-e1")
248250
.Case("0xd0c", "neoverse-n1")
249251
.Case("0xd49", "neoverse-n2")

‎llvm/unittests/TargetParser/TargetParserTest.cpp

Lines changed: 35 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1323,6 +1323,23 @@ INSTANTIATE_TEST_SUITE_P(
13231323
AArch64::AEK_PROFILE, AArch64::AEK_JSCVT,
13241324
AArch64::AEK_FCMA}),
13251325
"9.2-A"),
1326+
ARMCPUTestParams<AArch64::ExtensionBitset>(
1327+
"cortex-a725", "armv9.2-a", "crypto-neon-fp-armv8",
1328+
AArch64::ExtensionBitset(
1329+
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
1330+
AArch64::AEK_SVE, AArch64::AEK_SVE2,
1331+
AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
1332+
AArch64::AEK_LSE, AArch64::AEK_RDM,
1333+
AArch64::AEK_SIMD, AArch64::AEK_RCPC,
1334+
AArch64::AEK_RAS, AArch64::AEK_CRC,
1335+
AArch64::AEK_FP, AArch64::AEK_SB,
1336+
AArch64::AEK_SSBS, AArch64::AEK_MTE,
1337+
AArch64::AEK_FP16FML, AArch64::AEK_PAUTH,
1338+
AArch64::AEK_SVE2BITPERM, AArch64::AEK_FLAGM,
1339+
AArch64::AEK_PERFMON, AArch64::AEK_PREDRES,
1340+
AArch64::AEK_PROFILE, AArch64::AEK_JSCVT,
1341+
AArch64::AEK_FCMA}),
1342+
"9.2-A"),
13261343
ARMCPUTestParams<AArch64::ExtensionBitset>(
13271344
"neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
13281345
AArch64::ExtensionBitset(
@@ -1479,6 +1496,23 @@ INSTANTIATE_TEST_SUITE_P(
14791496
AArch64::AEK_PROFILE, AArch64::AEK_JSCVT,
14801497
AArch64::AEK_FCMA}),
14811498
"9.2-A"),
1499+
ARMCPUTestParams<AArch64::ExtensionBitset>(
1500+
"cortex-x925", "armv9.2-a", "crypto-neon-fp-armv8",
1501+
AArch64::ExtensionBitset(
1502+
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
1503+
AArch64::AEK_SVE, AArch64::AEK_SVE2,
1504+
AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
1505+
AArch64::AEK_LSE, AArch64::AEK_RDM,
1506+
AArch64::AEK_SIMD, AArch64::AEK_RCPC,
1507+
AArch64::AEK_RAS, AArch64::AEK_CRC,
1508+
AArch64::AEK_FP, AArch64::AEK_SB,
1509+
AArch64::AEK_SSBS, AArch64::AEK_MTE,
1510+
AArch64::AEK_FP16FML, AArch64::AEK_PAUTH,
1511+
AArch64::AEK_SVE2BITPERM, AArch64::AEK_FLAGM,
1512+
AArch64::AEK_PERFMON, AArch64::AEK_PREDRES,
1513+
AArch64::AEK_PROFILE, AArch64::AEK_JSCVT,
1514+
AArch64::AEK_FCMA}),
1515+
"9.2-A"),
14821516
ARMCPUTestParams<AArch64::ExtensionBitset>(
14831517
"cyclone", "armv8-a", "crypto-neon-fp-armv8",
14841518
AArch64::ExtensionBitset({AArch64::AEK_NONE, AArch64::AEK_AES,
@@ -1838,7 +1872,7 @@ INSTANTIATE_TEST_SUITE_P(
18381872
ARMCPUTestParams<AArch64::ExtensionBitset>::PrintToStringParamName);
18391873

18401874
// Note: number of CPUs includes aliases.
1841-
static constexpr unsigned NumAArch64CPUArchs = 77;
1875+
static constexpr unsigned NumAArch64CPUArchs = 79;
18421876

18431877
TEST(TargetParserTest, testAArch64CPUArchList) {
18441878
SmallVector<StringRef, NumAArch64CPUArchs> List;

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