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[FMV] Use lexicographic order of feature names when mangling. (#83464)
This decouples feature priorities from name mangling. Doing so will prevent ABI breakages in case we change the feature priorities. Formalized in ACLE here: ARM-software/acle#303.
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5 files changed

+99
-57
lines changed

5 files changed

+99
-57
lines changed

‎clang/lib/CodeGen/Targets/AArch64.cpp

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -882,13 +882,9 @@ void AArch64ABIInfo::appendAttributeMangling(StringRef AttrStr,
882882
for (auto &Feat : Features)
883883
Feat = Feat.trim();
884884

885-
// FIXME: It was brought up in #79316 that sorting the features which are
886-
// used for mangling based on their multiversion priority is not a good
887-
// practice. Changing the feature priorities will break the ABI. Perhaps
888-
// it would be preferable to perform a lexicographical sort instead.
889885
const TargetInfo &TI = CGT.getTarget();
890886
llvm::sort(Features, [&TI](const StringRef LHS, const StringRef RHS) {
891-
return TI.multiVersionSortPriority(LHS) < TI.multiVersionSortPriority(RHS);
887+
return LHS.compare(RHS) < 0;
892888
});
893889

894890
for (auto &Feat : Features)

‎clang/test/CodeGen/attr-target-clones-aarch64.c

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
4343
// CHECK: @ftc_inline3 = weak_odr ifunc i32 (), ptr @ftc_inline3.resolver
4444
//.
4545
// CHECK: Function Attrs: noinline nounwind optnone
46-
// CHECK-LABEL: @ftc._MlseMaes(
46+
// CHECK-LABEL: @ftc._MaesMlse(
4747
// CHECK-NEXT: entry:
4848
// CHECK-NEXT: ret i32 0
4949
//
@@ -69,7 +69,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
6969
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
7070
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
7171
// CHECK: resolver_return:
72-
// CHECK-NEXT: ret ptr @ftc._MlseMaes
72+
// CHECK-NEXT: ret ptr @ftc._MaesMlse
7373
// CHECK: resolver_else:
7474
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
7575
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 68719476736
@@ -89,7 +89,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
8989
//
9090
//
9191
// CHECK: Function Attrs: noinline nounwind optnone
92-
// CHECK-LABEL: @ftc_def._Msha2Mmemtag2(
92+
// CHECK-LABEL: @ftc_def._Mmemtag2Msha2(
9393
// CHECK-NEXT: entry:
9494
// CHECK-NEXT: ret i32 1
9595
//
@@ -109,7 +109,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
109109
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
110110
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
111111
// CHECK: resolver_return:
112-
// CHECK-NEXT: ret ptr @ftc_def._Msha2Mmemtag2
112+
// CHECK-NEXT: ret ptr @ftc_def._Mmemtag2Msha2
113113
// CHECK: resolver_else:
114114
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
115115
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4096
@@ -155,7 +155,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
155155
//
156156
//
157157
// CHECK: Function Attrs: noinline nounwind optnone
158-
// CHECK-LABEL: @ftc_dup2._MdotprodMcrc(
158+
// CHECK-LABEL: @ftc_dup2._McrcMdotprod(
159159
// CHECK-NEXT: entry:
160160
// CHECK-NEXT: ret i32 3
161161
//
@@ -175,7 +175,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
175175
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
176176
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
177177
// CHECK: resolver_return:
178-
// CHECK-NEXT: ret ptr @ftc_dup2._MdotprodMcrc
178+
// CHECK-NEXT: ret ptr @ftc_dup2._McrcMdotprod
179179
// CHECK: resolver_else:
180180
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
181181
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 256
@@ -239,7 +239,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
239239
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
240240
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
241241
// CHECK: resolver_return1:
242-
// CHECK-NEXT: ret ptr @ftc_inline1._MrcpcMpredres
242+
// CHECK-NEXT: ret ptr @ftc_inline1._MpredresMrcpc
243243
// CHECK: resolver_else2:
244244
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
245245
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 513
@@ -283,7 +283,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
283283
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
284284
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
285285
// CHECK: resolver_return:
286-
// CHECK-NEXT: ret ptr @ftc_inline3._MsveMsb
286+
// CHECK-NEXT: ret ptr @ftc_inline3._MsbMsve
287287
// CHECK: resolver_else:
288288
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
289289
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 1125899906842624
@@ -303,7 +303,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
303303
//
304304
//
305305
// CHECK: Function Attrs: noinline nounwind optnone
306-
// CHECK-LABEL: @ftc_inline1._MrcpcMpredres(
306+
// CHECK-LABEL: @ftc_inline1._MpredresMrcpc(
307307
// CHECK-NEXT: entry:
308308
// CHECK-NEXT: ret i32 1
309309
//
@@ -345,7 +345,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
345345
//
346346
//
347347
// CHECK: Function Attrs: noinline nounwind optnone
348-
// CHECK-LABEL: @ftc_inline3._MsveMsb(
348+
// CHECK-LABEL: @ftc_inline3._MsbMsve(
349349
// CHECK-NEXT: entry:
350350
// CHECK-NEXT: ret i32 3
351351
//

‎clang/test/CodeGen/attr-target-version.c

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -106,14 +106,14 @@ int hoo(void) {
106106
// CHECK: @fmv_c = weak_odr ifunc void (), ptr @fmv_c.resolver
107107
//.
108108
// CHECK: Function Attrs: noinline nounwind optnone
109-
// CHECK-LABEL: define {{[^@]+}}@fmv._MrngMflagmMfp16fml
109+
// CHECK-LABEL: define {{[^@]+}}@fmv._MflagmMfp16fmlMrng
110110
// CHECK-SAME: () #[[ATTR0:[0-9]+]] {
111111
// CHECK-NEXT: entry:
112112
// CHECK-NEXT: ret i32 1
113113
//
114114
//
115115
// CHECK: Function Attrs: noinline nounwind optnone
116-
// CHECK-LABEL: define {{[^@]+}}@fmv_one._MsimdMls64
116+
// CHECK-LABEL: define {{[^@]+}}@fmv_one._Mls64Msimd
117117
// CHECK-SAME: () #[[ATTR1:[0-9]+]] {
118118
// CHECK-NEXT: entry:
119119
// CHECK-NEXT: ret i32 1
@@ -147,7 +147,7 @@ int hoo(void) {
147147
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
148148
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
149149
// CHECK: resolver_return:
150-
// CHECK-NEXT: ret ptr @fmv._MrngMflagmMfp16fml
150+
// CHECK-NEXT: ret ptr @fmv._MflagmMfp16fmlMrng
151151
// CHECK: resolver_else:
152152
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
153153
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 72057594037927940
@@ -187,7 +187,7 @@ int hoo(void) {
187187
// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]]
188188
// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]
189189
// CHECK: resolver_return9:
190-
// CHECK-NEXT: ret ptr @fmv._MfpMaes
190+
// CHECK-NEXT: ret ptr @fmv._MaesMfp
191191
// CHECK: resolver_else10:
192192
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
193193
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 4224
@@ -218,12 +218,12 @@ int hoo(void) {
218218
//
219219
// CHECK-LABEL: define {{[^@]+}}@fmv_one.resolver() comdat {
220220
// CHECK-NEXT: resolver_entry:
221-
// CHECK-NEXT: ret ptr @fmv_one._MsimdMls64
221+
// CHECK-NEXT: ret ptr @fmv_one._Mls64Msimd
222222
//
223223
//
224224
// CHECK-LABEL: define {{[^@]+}}@fmv_two.resolver() comdat {
225225
// CHECK-NEXT: resolver_entry:
226-
// CHECK-NEXT: ret ptr @fmv_two._MsimdMfp16
226+
// CHECK-NEXT: ret ptr @fmv_two._Mfp16Msimd
227227
//
228228
//
229229
// CHECK-LABEL: define {{[^@]+}}@fmv_e.resolver() comdat {
@@ -266,47 +266,47 @@ int hoo(void) {
266266
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
267267
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
268268
// CHECK: resolver_return:
269-
// CHECK-NEXT: ret ptr @fmv_inline._Mfp16Mfp16MfcmaMsme
269+
// CHECK-NEXT: ret ptr @fmv_inline._MfcmaMfp16Mfp16Msme
270270
// CHECK: resolver_else:
271271
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
272272
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 864726312827224064
273273
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 864726312827224064
274274
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
275275
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
276276
// CHECK: resolver_return1:
277-
// CHECK-NEXT: ret ptr @fmv_inline._Mrcpc3Mmemtag3Mmops
277+
// CHECK-NEXT: ret ptr @fmv_inline._Mmemtag3MmopsMrcpc3
278278
// CHECK: resolver_else2:
279279
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
280280
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 893353197568
281281
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 893353197568
282282
// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
283283
// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
284284
// CHECK: resolver_return3:
285-
// CHECK-NEXT: ret ptr @fmv_inline._Msve2Msve2-pmull128Msve2-bitperm
285+
// CHECK-NEXT: ret ptr @fmv_inline._Msve2Msve2-bitpermMsve2-pmull128
286286
// CHECK: resolver_else4:
287287
// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
288288
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 34359773184
289289
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 34359773184
290290
// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]]
291291
// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
292292
// CHECK: resolver_return5:
293-
// CHECK-NEXT: ret ptr @fmv_inline._Msha1MpmullMf64mm
293+
// CHECK-NEXT: ret ptr @fmv_inline._Mf64mmMpmullMsha1
294294
// CHECK: resolver_else6:
295295
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
296296
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 17246986240
297297
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 17246986240
298298
// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]]
299299
// CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]]
300300
// CHECK: resolver_return7:
301-
// CHECK-NEXT: ret ptr @fmv_inline._Msha3Mi8mmMf32mm
301+
// CHECK-NEXT: ret ptr @fmv_inline._Mf32mmMi8mmMsha3
302302
// CHECK: resolver_else8:
303303
// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
304304
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 19791209299968
305305
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 19791209299968
306306
// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]]
307307
// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]
308308
// CHECK: resolver_return9:
309-
// CHECK-NEXT: ret ptr @fmv_inline._Msve2-sm4Mmemtag2
309+
// CHECK-NEXT: ret ptr @fmv_inline._Mmemtag2Msve2-sm4
310310
// CHECK: resolver_else10:
311311
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
312312
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 1236950581248
@@ -338,7 +338,7 @@ int hoo(void) {
338338
// CHECK-NEXT: [[TMP39:%.*]] = and i1 true, [[TMP38]]
339339
// CHECK-NEXT: br i1 [[TMP39]], label [[RESOLVER_RETURN17:%.*]], label [[RESOLVER_ELSE18:%.*]]
340340
// CHECK: resolver_return17:
341-
// CHECK-NEXT: ret ptr @fmv_inline._MrcpcMfrintts
341+
// CHECK-NEXT: ret ptr @fmv_inline._MfrinttsMrcpc
342342
// CHECK: resolver_else18:
343343
// CHECK-NEXT: [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
344344
// CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 8650752
@@ -362,15 +362,15 @@ int hoo(void) {
362362
// CHECK-NEXT: [[TMP51:%.*]] = and i1 true, [[TMP50]]
363363
// CHECK-NEXT: br i1 [[TMP51]], label [[RESOLVER_RETURN23:%.*]], label [[RESOLVER_ELSE24:%.*]]
364364
// CHECK: resolver_return23:
365-
// CHECK-NEXT: ret ptr @fmv_inline._MsimdMfp16fml
365+
// CHECK-NEXT: ret ptr @fmv_inline._Mfp16fmlMsimd
366366
// CHECK: resolver_else24:
367367
// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
368368
// CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 16400
369369
// CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 16400
370370
// CHECK-NEXT: [[TMP55:%.*]] = and i1 true, [[TMP54]]
371371
// CHECK-NEXT: br i1 [[TMP55]], label [[RESOLVER_RETURN25:%.*]], label [[RESOLVER_ELSE26:%.*]]
372372
// CHECK: resolver_return25:
373-
// CHECK-NEXT: ret ptr @fmv_inline._MdotprodMaes
373+
// CHECK-NEXT: ret ptr @fmv_inline._MaesMdotprod
374374
// CHECK: resolver_else26:
375375
// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
376376
// CHECK-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], 192
@@ -484,7 +484,7 @@ int hoo(void) {
484484
//
485485
//
486486
// CHECK: Function Attrs: noinline nounwind optnone
487-
// CHECK-LABEL: define {{[^@]+}}@fmv._MfpMaes
487+
// CHECK-LABEL: define {{[^@]+}}@fmv._MaesMfp
488488
// CHECK-SAME: () #[[ATTR1]] {
489489
// CHECK-NEXT: entry:
490490
// CHECK-NEXT: ret i32 6
@@ -547,7 +547,7 @@ int hoo(void) {
547547
//
548548
//
549549
// CHECK: Function Attrs: noinline nounwind optnone
550-
// CHECK-LABEL: define {{[^@]+}}@fmv_two._MsimdMfp16
550+
// CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp16Msimd
551551
// CHECK-SAME: () #[[ATTR1]] {
552552
// CHECK-NEXT: entry:
553553
// CHECK-NEXT: ret i32 4
@@ -568,21 +568,21 @@ int hoo(void) {
568568
//
569569
//
570570
// CHECK: Function Attrs: noinline nounwind optnone
571-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msha1MpmullMf64mm
571+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf64mmMpmullMsha1
572572
// CHECK-SAME: () #[[ATTR12:[0-9]+]] {
573573
// CHECK-NEXT: entry:
574574
// CHECK-NEXT: ret i32 1
575575
//
576576
//
577577
// CHECK: Function Attrs: noinline nounwind optnone
578-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mfp16Mfp16MfcmaMsme
578+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfcmaMfp16Mfp16Msme
579579
// CHECK-SAME: () #[[ATTR13:[0-9]+]] {
580580
// CHECK-NEXT: entry:
581581
// CHECK-NEXT: ret i32 2
582582
//
583583
//
584584
// CHECK: Function Attrs: noinline nounwind optnone
585-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msha3Mi8mmMf32mm
585+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf32mmMi8mmMsha3
586586
// CHECK-SAME: () #[[ATTR14:[0-9]+]] {
587587
// CHECK-NEXT: entry:
588588
// CHECK-NEXT: ret i32 12
@@ -610,7 +610,7 @@ int hoo(void) {
610610
//
611611
//
612612
// CHECK: Function Attrs: noinline nounwind optnone
613-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MrcpcMfrintts
613+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfrinttsMrcpc
614614
// CHECK-SAME: () #[[ATTR18:[0-9]+]] {
615615
// CHECK-NEXT: entry:
616616
// CHECK-NEXT: ret i32 3
@@ -631,35 +631,35 @@ int hoo(void) {
631631
//
632632
//
633633
// CHECK: Function Attrs: noinline nounwind optnone
634-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2Msve2-pmull128Msve2-bitperm
634+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2Msve2-bitpermMsve2-pmull128
635635
// CHECK-SAME: () #[[ATTR21:[0-9]+]] {
636636
// CHECK-NEXT: entry:
637637
// CHECK-NEXT: ret i32 9
638638
//
639639
//
640640
// CHECK: Function Attrs: noinline nounwind optnone
641-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2-sm4Mmemtag2
641+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mmemtag2Msve2-sm4
642642
// CHECK-SAME: () #[[ATTR22:[0-9]+]] {
643643
// CHECK-NEXT: entry:
644644
// CHECK-NEXT: ret i32 10
645645
//
646646
//
647647
// CHECK: Function Attrs: noinline nounwind optnone
648-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mrcpc3Mmemtag3Mmops
648+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mmemtag3MmopsMrcpc3
649649
// CHECK-SAME: () #[[ATTR23:[0-9]+]] {
650650
// CHECK-NEXT: entry:
651651
// CHECK-NEXT: ret i32 11
652652
//
653653
//
654654
// CHECK: Function Attrs: noinline nounwind optnone
655-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MdotprodMaes
655+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MaesMdotprod
656656
// CHECK-SAME: () #[[ATTR6]] {
657657
// CHECK-NEXT: entry:
658658
// CHECK-NEXT: ret i32 13
659659
//
660660
//
661661
// CHECK: Function Attrs: noinline nounwind optnone
662-
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MsimdMfp16fml
662+
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mfp16fmlMsimd
663663
// CHECK-SAME: () #[[ATTR7]] {
664664
// CHECK-NEXT: entry:
665665
// CHECK-NEXT: ret i32 14

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