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[X86] Remove SlowDivide tuning from GRTTuning (#84676)
The DIV32/64 throughput was improved since Goldmont in the Atom architecture. The Alder Lake-E shows similar number too. So we shouldn't add such tunings to Gracemont and later products. Checked from Agner Fog's table and uops.info.
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llvm/lib/Target/X86/X86.td

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@@ -1237,8 +1237,6 @@ def ProcessorFeatures {
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// Gracemont
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list<SubtargetFeature> GRTTuning = [TuningMacroFusion,
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TuningSlow3OpsLEA,
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TuningSlowDivide32,
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TuningSlowDivide64,
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TuningFastScalarFSQRT,
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TuningFastVectorFSQRT,
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TuningFast15ByteNOP,

llvm/test/CodeGen/X86/bypass-slow-division-tune.ll

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@@ -4,6 +4,8 @@
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64 < %s | FileCheck -check-prefixes=CHECK,REST,X64 %s
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=silvermont < %s | FileCheck -check-prefixes=CHECK,REST,SLM %s
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=skylake < %s | FileCheck -check-prefixes=CHECK,REST,SKL %s
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=goldmont < %s | FileCheck -check-prefixes=CHECK,REST,GMT %s
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=gracemont < %s | FileCheck -check-prefixes=CHECK,REST,GMT %s
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; RUN: llc -profile-summary-huge-working-set-size-threshold=1 -mtriple=x86_64-unknown-linux-gnu -mcpu=skylake < %s | FileCheck -check-prefixes=HUGEWS %s
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; Verify that div32 is bypassed only for Atoms.
@@ -117,6 +119,13 @@ define i64 @div64(i64 %a, i64 %b) {
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; SKL-NEXT: # kill: def $eax killed $eax def $rax
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; SKL-NEXT: retq
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;
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; GMT-LABEL: div64:
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; GMT: # %bb.0: # %entry
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; GMT-NEXT: movq %rdi, %rax
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; GMT-NEXT: cqto
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; GMT-NEXT: idivq %rsi
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; GMT-NEXT: retq
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;
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; HUGEWS-LABEL: div64:
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; HUGEWS: # %bb.0: # %entry
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; HUGEWS-NEXT: movq %rdi, %rax
@@ -240,6 +249,13 @@ define i64 @div64_hugews(i64 %a, i64 %b) {
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; SKL-NEXT: # kill: def $eax killed $eax def $rax
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; SKL-NEXT: retq
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;
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; GMT-LABEL: div64_hugews:
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; GMT: # %bb.0:
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; GMT-NEXT: movq %rdi, %rax
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; GMT-NEXT: cqto
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; GMT-NEXT: idivq %rsi
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; GMT-NEXT: retq
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;
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; HUGEWS-LABEL: div64_hugews:
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; HUGEWS: # %bb.0:
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; HUGEWS-NEXT: movq %rdi, %rax

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