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[RISCV] Prefer whole register loads and stores when VL=VLMAX (#75531)
If we're lowering a fixed length vector load or store which happens to exactly VLEN in size (when VLEN is exactly known), we can use a whole register load or store instead of the unit strided variants. This doesn't require a vsetvli in some cases, allows additional flexibility of vsetvli cases in others, and doesn't have a runtime dependency on the value of VL.
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7 files changed

+171
-90
lines changed

7 files changed

+171
-90
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24178,6 +24178,10 @@ static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) {
2417824178

2417924179
unsigned Index = Extract->getConstantOperandVal(1);
2418024180
unsigned NumElts = VT.getVectorMinNumElements();
24181+
// A fixed length vector being extracted from a scalable vector
24182+
// may not be any *smaller* than the scalable one.
24183+
if (Index == 0 && NumElts >= Ld->getValueType(0).getVectorMinNumElements())
24184+
return SDValue();
2418124185

2418224186
// The definition of EXTRACT_SUBVECTOR states that the index must be a
2418324187
// multiple of the minimum number of elements in the result type.

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 26 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9838,6 +9838,19 @@ RISCVTargetLowering::lowerFixedLengthVectorLoadToRVV(SDValue Op,
98389838
MVT XLenVT = Subtarget.getXLenVT();
98399839
MVT ContainerVT = getContainerForFixedLengthVector(VT);
98409840

9841+
// If we know the exact VLEN and our fixed length vector completely fills
9842+
// the container, use a whole register load instead.
9843+
const auto [MinVLMAX, MaxVLMAX] =
9844+
RISCVTargetLowering::computeVLMAXBounds(ContainerVT, Subtarget);
9845+
if (MinVLMAX == MaxVLMAX && MinVLMAX == VT.getVectorNumElements() &&
9846+
getLMUL1VT(ContainerVT).bitsLE(ContainerVT)) {
9847+
SDValue NewLoad =
9848+
DAG.getLoad(ContainerVT, DL, Load->getChain(), Load->getBasePtr(),
9849+
Load->getMemOperand());
9850+
SDValue Result = convertFromScalableVector(VT, NewLoad, DAG, Subtarget);
9851+
return DAG.getMergeValues({Result, NewLoad.getValue(1)}, DL);
9852+
}
9853+
98419854
SDValue VL = getVLOp(VT.getVectorNumElements(), ContainerVT, DL, DAG, Subtarget);
98429855

98439856
bool IsMaskOp = VT.getVectorElementType() == MVT::i1;
@@ -9882,12 +9895,22 @@ RISCVTargetLowering::lowerFixedLengthVectorStoreToRVV(SDValue Op,
98829895

98839896
MVT ContainerVT = getContainerForFixedLengthVector(VT);
98849897

9885-
SDValue VL = getVLOp(VT.getVectorNumElements(), ContainerVT, DL, DAG,
9886-
Subtarget);
9887-
98889898
SDValue NewValue =
98899899
convertToScalableVector(ContainerVT, StoreVal, DAG, Subtarget);
98909900

9901+
9902+
// If we know the exact VLEN and our fixed length vector completely fills
9903+
// the container, use a whole register store instead.
9904+
const auto [MinVLMAX, MaxVLMAX] =
9905+
RISCVTargetLowering::computeVLMAXBounds(ContainerVT, Subtarget);
9906+
if (MinVLMAX == MaxVLMAX && MinVLMAX == VT.getVectorNumElements() &&
9907+
getLMUL1VT(ContainerVT).bitsLE(ContainerVT))
9908+
return DAG.getStore(Store->getChain(), DL, NewValue, Store->getBasePtr(),
9909+
Store->getMemOperand());
9910+
9911+
SDValue VL = getVLOp(VT.getVectorNumElements(), ContainerVT, DL, DAG,
9912+
Subtarget);
9913+
98919914
bool IsMaskOp = VT.getVectorElementType() == MVT::i1;
98929915
SDValue IntID = DAG.getTargetConstant(
98939916
IsMaskOp ? Intrinsic::riscv_vsm : Intrinsic::riscv_vse, DL, XLenVT);

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll

Lines changed: 118 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -63,93 +63,145 @@ define void @extract_v2i8_v8i8_6(ptr %x, ptr %y) {
6363
}
6464

6565
define void @extract_v1i32_v8i32_4(ptr %x, ptr %y) {
66-
; CHECK-LABEL: extract_v1i32_v8i32_4:
67-
; CHECK: # %bb.0:
68-
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
69-
; CHECK-NEXT: vle32.v v8, (a0)
70-
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma
71-
; CHECK-NEXT: vslidedown.vi v8, v8, 4
72-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
73-
; CHECK-NEXT: vse32.v v8, (a1)
74-
; CHECK-NEXT: ret
66+
; CHECK-V-LABEL: extract_v1i32_v8i32_4:
67+
; CHECK-V: # %bb.0:
68+
; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
69+
; CHECK-V-NEXT: vle32.v v8, (a0)
70+
; CHECK-V-NEXT: vsetivli zero, 1, e32, m2, ta, ma
71+
; CHECK-V-NEXT: vslidedown.vi v8, v8, 4
72+
; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
73+
; CHECK-V-NEXT: vse32.v v8, (a1)
74+
; CHECK-V-NEXT: ret
75+
;
76+
; CHECK-KNOWNVLEN128-LABEL: extract_v1i32_v8i32_4:
77+
; CHECK-KNOWNVLEN128: # %bb.0:
78+
; CHECK-KNOWNVLEN128-NEXT: vl2re32.v v8, (a0)
79+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 1, e32, m2, ta, ma
80+
; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v8, 4
81+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
82+
; CHECK-KNOWNVLEN128-NEXT: vse32.v v8, (a1)
83+
; CHECK-KNOWNVLEN128-NEXT: ret
7584
%a = load <8 x i32>, ptr %x
7685
%c = call <1 x i32> @llvm.vector.extract.v1i32.v8i32(<8 x i32> %a, i64 4)
7786
store <1 x i32> %c, ptr %y
7887
ret void
7988
}
8089

8190
define void @extract_v1i32_v8i32_5(ptr %x, ptr %y) {
82-
; CHECK-LABEL: extract_v1i32_v8i32_5:
83-
; CHECK: # %bb.0:
84-
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
85-
; CHECK-NEXT: vle32.v v8, (a0)
86-
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma
87-
; CHECK-NEXT: vslidedown.vi v8, v8, 5
88-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
89-
; CHECK-NEXT: vse32.v v8, (a1)
90-
; CHECK-NEXT: ret
91+
; CHECK-V-LABEL: extract_v1i32_v8i32_5:
92+
; CHECK-V: # %bb.0:
93+
; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
94+
; CHECK-V-NEXT: vle32.v v8, (a0)
95+
; CHECK-V-NEXT: vsetivli zero, 1, e32, m2, ta, ma
96+
; CHECK-V-NEXT: vslidedown.vi v8, v8, 5
97+
; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
98+
; CHECK-V-NEXT: vse32.v v8, (a1)
99+
; CHECK-V-NEXT: ret
100+
;
101+
; CHECK-KNOWNVLEN128-LABEL: extract_v1i32_v8i32_5:
102+
; CHECK-KNOWNVLEN128: # %bb.0:
103+
; CHECK-KNOWNVLEN128-NEXT: vl2re32.v v8, (a0)
104+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 1, e32, m2, ta, ma
105+
; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v8, 5
106+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
107+
; CHECK-KNOWNVLEN128-NEXT: vse32.v v8, (a1)
108+
; CHECK-KNOWNVLEN128-NEXT: ret
91109
%a = load <8 x i32>, ptr %x
92110
%c = call <1 x i32> @llvm.vector.extract.v1i32.v8i32(<8 x i32> %a, i64 5)
93111
store <1 x i32> %c, ptr %y
94112
ret void
95113
}
96114

97115
define void @extract_v2i32_v8i32_0(ptr %x, ptr %y) {
98-
; CHECK-LABEL: extract_v2i32_v8i32_0:
99-
; CHECK: # %bb.0:
100-
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
101-
; CHECK-NEXT: vle32.v v8, (a0)
102-
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
103-
; CHECK-NEXT: vse32.v v8, (a1)
104-
; CHECK-NEXT: ret
116+
; CHECK-V-LABEL: extract_v2i32_v8i32_0:
117+
; CHECK-V: # %bb.0:
118+
; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
119+
; CHECK-V-NEXT: vle32.v v8, (a0)
120+
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
121+
; CHECK-V-NEXT: vse32.v v8, (a1)
122+
; CHECK-V-NEXT: ret
123+
;
124+
; CHECK-KNOWNVLEN128-LABEL: extract_v2i32_v8i32_0:
125+
; CHECK-KNOWNVLEN128: # %bb.0:
126+
; CHECK-KNOWNVLEN128-NEXT: vl2re32.v v8, (a0)
127+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
128+
; CHECK-KNOWNVLEN128-NEXT: vse32.v v8, (a1)
129+
; CHECK-KNOWNVLEN128-NEXT: ret
105130
%a = load <8 x i32>, ptr %x
106131
%c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 0)
107132
store <2 x i32> %c, ptr %y
108133
ret void
109134
}
110135

111136
define void @extract_v2i32_v8i32_2(ptr %x, ptr %y) {
112-
; CHECK-LABEL: extract_v2i32_v8i32_2:
113-
; CHECK: # %bb.0:
114-
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
115-
; CHECK-NEXT: vle32.v v8, (a0)
116-
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
117-
; CHECK-NEXT: vslidedown.vi v8, v8, 2
118-
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
119-
; CHECK-NEXT: vse32.v v8, (a1)
120-
; CHECK-NEXT: ret
137+
; CHECK-V-LABEL: extract_v2i32_v8i32_2:
138+
; CHECK-V: # %bb.0:
139+
; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
140+
; CHECK-V-NEXT: vle32.v v8, (a0)
141+
; CHECK-V-NEXT: vsetivli zero, 2, e32, m1, ta, ma
142+
; CHECK-V-NEXT: vslidedown.vi v8, v8, 2
143+
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
144+
; CHECK-V-NEXT: vse32.v v8, (a1)
145+
; CHECK-V-NEXT: ret
146+
;
147+
; CHECK-KNOWNVLEN128-LABEL: extract_v2i32_v8i32_2:
148+
; CHECK-KNOWNVLEN128: # %bb.0:
149+
; CHECK-KNOWNVLEN128-NEXT: vl2re32.v v8, (a0)
150+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, m1, ta, ma
151+
; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v8, 2
152+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
153+
; CHECK-KNOWNVLEN128-NEXT: vse32.v v8, (a1)
154+
; CHECK-KNOWNVLEN128-NEXT: ret
121155
%a = load <8 x i32>, ptr %x
122156
%c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 2)
123157
store <2 x i32> %c, ptr %y
124158
ret void
125159
}
126160

127161
define void @extract_v2i32_v8i32_4(ptr %x, ptr %y) {
128-
; CHECK-LABEL: extract_v2i32_v8i32_4:
129-
; CHECK: # %bb.0:
130-
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
131-
; CHECK-NEXT: vle32.v v8, (a0)
132-
; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, ma
133-
; CHECK-NEXT: vslidedown.vi v8, v8, 4
134-
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
135-
; CHECK-NEXT: vse32.v v8, (a1)
136-
; CHECK-NEXT: ret
162+
; CHECK-V-LABEL: extract_v2i32_v8i32_4:
163+
; CHECK-V: # %bb.0:
164+
; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
165+
; CHECK-V-NEXT: vle32.v v8, (a0)
166+
; CHECK-V-NEXT: vsetivli zero, 2, e32, m2, ta, ma
167+
; CHECK-V-NEXT: vslidedown.vi v8, v8, 4
168+
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
169+
; CHECK-V-NEXT: vse32.v v8, (a1)
170+
; CHECK-V-NEXT: ret
171+
;
172+
; CHECK-KNOWNVLEN128-LABEL: extract_v2i32_v8i32_4:
173+
; CHECK-KNOWNVLEN128: # %bb.0:
174+
; CHECK-KNOWNVLEN128-NEXT: vl2re32.v v8, (a0)
175+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, m2, ta, ma
176+
; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v8, 4
177+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
178+
; CHECK-KNOWNVLEN128-NEXT: vse32.v v8, (a1)
179+
; CHECK-KNOWNVLEN128-NEXT: ret
137180
%a = load <8 x i32>, ptr %x
138181
%c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 4)
139182
store <2 x i32> %c, ptr %y
140183
ret void
141184
}
142185

143186
define void @extract_v2i32_v8i32_6(ptr %x, ptr %y) {
144-
; CHECK-LABEL: extract_v2i32_v8i32_6:
145-
; CHECK: # %bb.0:
146-
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
147-
; CHECK-NEXT: vle32.v v8, (a0)
148-
; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, ma
149-
; CHECK-NEXT: vslidedown.vi v8, v8, 6
150-
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
151-
; CHECK-NEXT: vse32.v v8, (a1)
152-
; CHECK-NEXT: ret
187+
; CHECK-V-LABEL: extract_v2i32_v8i32_6:
188+
; CHECK-V: # %bb.0:
189+
; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
190+
; CHECK-V-NEXT: vle32.v v8, (a0)
191+
; CHECK-V-NEXT: vsetivli zero, 2, e32, m2, ta, ma
192+
; CHECK-V-NEXT: vslidedown.vi v8, v8, 6
193+
; CHECK-V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
194+
; CHECK-V-NEXT: vse32.v v8, (a1)
195+
; CHECK-V-NEXT: ret
196+
;
197+
; CHECK-KNOWNVLEN128-LABEL: extract_v2i32_v8i32_6:
198+
; CHECK-KNOWNVLEN128: # %bb.0:
199+
; CHECK-KNOWNVLEN128-NEXT: vl2re32.v v8, (a0)
200+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, m2, ta, ma
201+
; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v8, 6
202+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
203+
; CHECK-KNOWNVLEN128-NEXT: vse32.v v8, (a1)
204+
; CHECK-KNOWNVLEN128-NEXT: ret
153205
%a = load <8 x i32>, ptr %x
154206
%c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 6)
155207
store <2 x i32> %c, ptr %y
@@ -271,13 +323,20 @@ define void @extract_v2i8_nxv2i8_6(<vscale x 2 x i8> %x, ptr %y) {
271323
}
272324

273325
define void @extract_v8i32_nxv16i32_8(<vscale x 16 x i32> %x, ptr %y) {
274-
; CHECK-LABEL: extract_v8i32_nxv16i32_8:
275-
; CHECK: # %bb.0:
276-
; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
277-
; CHECK-NEXT: vslidedown.vi v8, v8, 8
278-
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
279-
; CHECK-NEXT: vse32.v v8, (a0)
280-
; CHECK-NEXT: ret
326+
; CHECK-V-LABEL: extract_v8i32_nxv16i32_8:
327+
; CHECK-V: # %bb.0:
328+
; CHECK-V-NEXT: vsetivli zero, 8, e32, m4, ta, ma
329+
; CHECK-V-NEXT: vslidedown.vi v8, v8, 8
330+
; CHECK-V-NEXT: vsetivli zero, 8, e32, m2, ta, ma
331+
; CHECK-V-NEXT: vse32.v v8, (a0)
332+
; CHECK-V-NEXT: ret
333+
;
334+
; CHECK-KNOWNVLEN128-LABEL: extract_v8i32_nxv16i32_8:
335+
; CHECK-KNOWNVLEN128: # %bb.0:
336+
; CHECK-KNOWNVLEN128-NEXT: vsetivli zero, 8, e32, m4, ta, ma
337+
; CHECK-KNOWNVLEN128-NEXT: vslidedown.vi v8, v8, 8
338+
; CHECK-KNOWNVLEN128-NEXT: vs2r.v v8, (a0)
339+
; CHECK-KNOWNVLEN128-NEXT: ret
281340
%c = call <8 x i32> @llvm.vector.extract.v8i32.nxv16i32(<vscale x 16 x i32> %x, i64 8)
282341
store <8 x i32> %c, ptr %y
283342
ret void

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1141,10 +1141,10 @@ define float @extractelt_fdiv_v4f32(<4 x float> %x) {
11411141
define i32 @extractelt_v16i32_idx7_exact_vlen(ptr %x) nounwind vscale_range(2,2) {
11421142
; CHECK-LABEL: extractelt_v16i32_idx7_exact_vlen:
11431143
; CHECK: # %bb.0:
1144-
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
1145-
; CHECK-NEXT: vle32.v v8, (a0)
1144+
; CHECK-NEXT: addi a0, a0, 16
1145+
; CHECK-NEXT: vl1re32.v v8, (a0)
11461146
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
1147-
; CHECK-NEXT: vslidedown.vi v8, v9, 3
1147+
; CHECK-NEXT: vslidedown.vi v8, v8, 3
11481148
; CHECK-NEXT: vmv.x.s a0, v8
11491149
; CHECK-NEXT: ret
11501150
%a = load <16 x i32>, ptr %x
@@ -1155,10 +1155,10 @@ define i32 @extractelt_v16i32_idx7_exact_vlen(ptr %x) nounwind vscale_range(2,2)
11551155
define i32 @extractelt_v16i32_idx15_exact_vlen(ptr %x) nounwind vscale_range(2,2) {
11561156
; CHECK-LABEL: extractelt_v16i32_idx15_exact_vlen:
11571157
; CHECK: # %bb.0:
1158-
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
1159-
; CHECK-NEXT: vle32.v v8, (a0)
1158+
; CHECK-NEXT: addi a0, a0, 48
1159+
; CHECK-NEXT: vl1re32.v v8, (a0)
11601160
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
1161-
; CHECK-NEXT: vslidedown.vi v8, v11, 3
1161+
; CHECK-NEXT: vslidedown.vi v8, v8, 3
11621162
; CHECK-NEXT: vmv.x.s a0, v8
11631163
; CHECK-NEXT: ret
11641164
%a = load <16 x i32>, ptr %x

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -140,8 +140,7 @@ define <6 x i1> @load_v6i1(ptr %p) {
140140
define <4 x i32> @exact_vlen_i32_m1(ptr %p) vscale_range(2,2) {
141141
; CHECK-LABEL: exact_vlen_i32_m1:
142142
; CHECK: # %bb.0:
143-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
144-
; CHECK-NEXT: vle32.v v8, (a0)
143+
; CHECK-NEXT: vl1re32.v v8, (a0)
145144
; CHECK-NEXT: ret
146145
%v = load <4 x i32>, ptr %p
147146
ret <4 x i32> %v
@@ -150,8 +149,7 @@ define <4 x i32> @exact_vlen_i32_m1(ptr %p) vscale_range(2,2) {
150149
define <16 x i8> @exact_vlen_i8_m1(ptr %p) vscale_range(2,2) {
151150
; CHECK-LABEL: exact_vlen_i8_m1:
152151
; CHECK: # %bb.0:
153-
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
154-
; CHECK-NEXT: vle8.v v8, (a0)
152+
; CHECK-NEXT: vl1r.v v8, (a0)
155153
; CHECK-NEXT: ret
156154
%v = load <16 x i8>, ptr %p
157155
ret <16 x i8> %v
@@ -160,8 +158,7 @@ define <16 x i8> @exact_vlen_i8_m1(ptr %p) vscale_range(2,2) {
160158
define <32 x i8> @exact_vlen_i8_m2(ptr %p) vscale_range(2,2) {
161159
; CHECK-LABEL: exact_vlen_i8_m2:
162160
; CHECK: # %bb.0:
163-
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
164-
; CHECK-NEXT: vle8.v v8, (a0)
161+
; CHECK-NEXT: vl2r.v v8, (a0)
165162
; CHECK-NEXT: ret
166163
%v = load <32 x i8>, ptr %p
167164
ret <32 x i8> %v
@@ -170,8 +167,7 @@ define <32 x i8> @exact_vlen_i8_m2(ptr %p) vscale_range(2,2) {
170167
define <128 x i8> @exact_vlen_i8_m8(ptr %p) vscale_range(2,2) {
171168
; CHECK-LABEL: exact_vlen_i8_m8:
172169
; CHECK: # %bb.0:
173-
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
174-
; CHECK-NEXT: vle8.v v8, (a0)
170+
; CHECK-NEXT: vl8r.v v8, (a0)
175171
; CHECK-NEXT: ret
176172
%v = load <128 x i8>, ptr %p
177173
ret <128 x i8> %v
@@ -180,8 +176,7 @@ define <128 x i8> @exact_vlen_i8_m8(ptr %p) vscale_range(2,2) {
180176
define <16 x i64> @exact_vlen_i64_m8(ptr %p) vscale_range(2,2) {
181177
; CHECK-LABEL: exact_vlen_i64_m8:
182178
; CHECK: # %bb.0:
183-
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
184-
; CHECK-NEXT: vle64.v v8, (a0)
179+
; CHECK-NEXT: vl8re64.v v8, (a0)
185180
; CHECK-NEXT: ret
186181
%v = load <16 x i64>, ptr %p
187182
ret <16 x i64> %v

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