@@ -66,6 +66,11 @@ class AArch64ExpandPseudo : public MachineFunctionPass {
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bool expandMBB (MachineBasicBlock &MBB);
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bool expandMI (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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+ bool expandMultiVecPseudo (MachineBasicBlock &MBB,
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+ MachineBasicBlock::iterator MBBI,
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+ TargetRegisterClass ContiguousClass,
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+ TargetRegisterClass StridedClass,
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+ unsigned ContiguousOpc, unsigned StridedOpc);
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bool expandMOVImm (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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unsigned BitSize);
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@@ -1038,6 +1043,35 @@ AArch64ExpandPseudo::expandCondSMToggle(MachineBasicBlock &MBB,
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return EndBB;
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}
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+ bool AArch64ExpandPseudo::expandMultiVecPseudo (
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+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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+ TargetRegisterClass ContiguousClass, TargetRegisterClass StridedClass,
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+ unsigned ContiguousOp, unsigned StridedOpc) {
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+ MachineInstr &MI = *MBBI;
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+ Register Tuple = MI.getOperand (0 ).getReg ();
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+
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+ auto ContiguousRange = ContiguousClass.getRegisters ();
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+ auto StridedRange = StridedClass.getRegisters ();
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+ unsigned Opc;
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+ if ((std::find (ContiguousRange.begin (), ContiguousRange.end (),
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+ Tuple.asMCReg ()) != std::end (ContiguousRange))) {
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+ Opc = ContiguousOp;
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+ } else if ((std::find (StridedRange.begin (), StridedRange.end (),
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+ Tuple.asMCReg ()) != std::end (StridedRange))) {
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+ Opc = StridedOpc;
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+ } else
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+ llvm_unreachable (" Cannot expand Multi-Vector pseudo" );
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+
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+ MachineInstrBuilder MIB = BuildMI (MBB, MBBI, MI.getDebugLoc (), TII->get (Opc))
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+ .add (MI.getOperand (0 ))
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+ .add (MI.getOperand (1 ))
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+ .add (MI.getOperand (2 ))
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+ .add (MI.getOperand (3 ));
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+ transferImpOps (MI, MIB, MIB);
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+ MI.eraseFromParent ();
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+ return true ;
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+ }
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+
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// / If MBBI references a pseudo instruction that should be expanded here,
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// / do the expansion and return true. Otherwise return false.
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bool AArch64ExpandPseudo::expandMI (MachineBasicBlock &MBB,
@@ -1492,6 +1526,134 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
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MI.eraseFromParent ();
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return true ;
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}
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+ case AArch64::LD1B_2Z_IMM_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
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+ AArch64::LD1B_2Z_IMM, AArch64::LD1B_2Z_STRIDED_IMM);
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+ case AArch64::LD1H_2Z_IMM_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
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+ AArch64::LD1H_2Z_IMM, AArch64::LD1H_2Z_STRIDED_IMM);
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+ case AArch64::LD1W_2Z_IMM_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
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+ AArch64::LD1W_2Z_IMM, AArch64::LD1W_2Z_STRIDED_IMM);
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+ case AArch64::LD1D_2Z_IMM_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
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+ AArch64::LD1D_2Z_IMM, AArch64::LD1D_2Z_STRIDED_IMM);
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+ case AArch64::LDNT1B_2Z_IMM_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
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+ AArch64::LDNT1B_2Z_IMM, AArch64::LDNT1B_2Z_STRIDED_IMM);
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+ case AArch64::LDNT1H_2Z_IMM_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
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+ AArch64::LDNT1H_2Z_IMM, AArch64::LDNT1H_2Z_STRIDED_IMM);
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+ case AArch64::LDNT1W_2Z_IMM_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
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+ AArch64::LDNT1W_2Z_IMM, AArch64::LDNT1W_2Z_STRIDED_IMM);
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+ case AArch64::LDNT1D_2Z_IMM_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
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+ AArch64::LDNT1D_2Z_IMM, AArch64::LDNT1D_2Z_STRIDED_IMM);
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+ case AArch64::LD1B_2Z_PSEUDO:
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+ return expandMultiVecPseudo (MBB, MBBI, AArch64::ZPR2RegClass,
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+ AArch64::ZPR2StridedRegClass, AArch64::LD1B_2Z,
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+ AArch64::LD1B_2Z_STRIDED);
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+ case AArch64::LD1H_2Z_PSEUDO:
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+ return expandMultiVecPseudo (MBB, MBBI, AArch64::ZPR2RegClass,
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+ AArch64::ZPR2StridedRegClass, AArch64::LD1H_2Z,
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+ AArch64::LD1H_2Z_STRIDED);
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+ case AArch64::LD1W_2Z_PSEUDO:
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+ return expandMultiVecPseudo (MBB, MBBI, AArch64::ZPR2RegClass,
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+ AArch64::ZPR2StridedRegClass, AArch64::LD1W_2Z,
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+ AArch64::LD1W_2Z_STRIDED);
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+ case AArch64::LD1D_2Z_PSEUDO:
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+ return expandMultiVecPseudo (MBB, MBBI, AArch64::ZPR2RegClass,
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+ AArch64::ZPR2StridedRegClass, AArch64::LD1D_2Z,
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+ AArch64::LD1D_2Z_STRIDED);
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+ case AArch64::LDNT1B_2Z_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
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+ AArch64::LDNT1B_2Z, AArch64::LDNT1B_2Z_STRIDED);
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+ case AArch64::LDNT1H_2Z_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
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+ AArch64::LDNT1H_2Z, AArch64::LDNT1H_2Z_STRIDED);
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+ case AArch64::LDNT1W_2Z_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
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+ AArch64::LDNT1W_2Z, AArch64::LDNT1W_2Z_STRIDED);
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+ case AArch64::LDNT1D_2Z_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR2RegClass, AArch64::ZPR2StridedRegClass,
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+ AArch64::LDNT1D_2Z, AArch64::LDNT1D_2Z_STRIDED);
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+ case AArch64::LD1B_4Z_IMM_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
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+ AArch64::LD1B_4Z_IMM, AArch64::LD1B_4Z_STRIDED_IMM);
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+ case AArch64::LD1H_4Z_IMM_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
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+ AArch64::LD1H_4Z_IMM, AArch64::LD1H_4Z_STRIDED_IMM);
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+ case AArch64::LD1W_4Z_IMM_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
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+ AArch64::LD1W_4Z_IMM, AArch64::LD1W_4Z_STRIDED_IMM);
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+ case AArch64::LD1D_4Z_IMM_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
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+ AArch64::LD1D_4Z_IMM, AArch64::LD1D_4Z_STRIDED_IMM);
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+ case AArch64::LDNT1B_4Z_IMM_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
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+ AArch64::LDNT1B_4Z_IMM, AArch64::LDNT1B_4Z_STRIDED_IMM);
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+ case AArch64::LDNT1H_4Z_IMM_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
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+ AArch64::LDNT1H_4Z_IMM, AArch64::LDNT1H_4Z_STRIDED_IMM);
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+ case AArch64::LDNT1W_4Z_IMM_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
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+ AArch64::LDNT1W_4Z_IMM, AArch64::LDNT1W_4Z_STRIDED_IMM);
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+ case AArch64::LDNT1D_4Z_IMM_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
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+ AArch64::LDNT1D_4Z_IMM, AArch64::LDNT1D_4Z_STRIDED_IMM);
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+ case AArch64::LD1B_4Z_PSEUDO:
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+ return expandMultiVecPseudo (MBB, MBBI, AArch64::ZPR4RegClass,
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+ AArch64::ZPR4StridedRegClass, AArch64::LD1B_4Z,
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+ AArch64::LD1B_4Z_STRIDED);
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+ case AArch64::LD1H_4Z_PSEUDO:
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+ return expandMultiVecPseudo (MBB, MBBI, AArch64::ZPR4RegClass,
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+ AArch64::ZPR4StridedRegClass, AArch64::LD1H_4Z,
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+ AArch64::LD1H_4Z_STRIDED);
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+ case AArch64::LD1W_4Z_PSEUDO:
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+ return expandMultiVecPseudo (MBB, MBBI, AArch64::ZPR4RegClass,
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+ AArch64::ZPR4StridedRegClass, AArch64::LD1W_4Z,
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+ AArch64::LD1W_4Z_STRIDED);
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+ case AArch64::LD1D_4Z_PSEUDO:
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+ return expandMultiVecPseudo (MBB, MBBI, AArch64::ZPR4RegClass,
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+ AArch64::ZPR4StridedRegClass, AArch64::LD1D_4Z,
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+ AArch64::LD1D_4Z_STRIDED);
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+ case AArch64::LDNT1B_4Z_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
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+ AArch64::LDNT1B_4Z, AArch64::LDNT1B_4Z_STRIDED);
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+ case AArch64::LDNT1H_4Z_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
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+ AArch64::LDNT1H_4Z, AArch64::LDNT1H_4Z_STRIDED);
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+ case AArch64::LDNT1W_4Z_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
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+ AArch64::LDNT1W_4Z, AArch64::LDNT1W_4Z_STRIDED);
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+ case AArch64::LDNT1D_4Z_PSEUDO:
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+ return expandMultiVecPseudo (
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+ MBB, MBBI, AArch64::ZPR4RegClass, AArch64::ZPR4StridedRegClass,
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+ AArch64::LDNT1D_4Z, AArch64::LDNT1D_4Z_STRIDED);
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}
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return false ;
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}
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