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[DAG] canCreateUndefOrPoison – mark fneg/fadd/fsub/fmul/fdiv/frem as not poison generating
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‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5639,6 +5639,12 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
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case ISD::ADD:
56405640
case ISD::SUB:
56415641
case ISD::MUL:
5642+
case ISD::FNEG:
5643+
case ISD::FADD:
5644+
case ISD::FSUB:
5645+
case ISD::FMUL:
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case ISD::FDIV:
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case ISD::FREM:
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// No poison except from flags (which is handled above)
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return false;
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‎llvm/test/CodeGen/AMDGPU/freeze-binary.ll

Lines changed: 282 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,282 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefix GFX11
3+
define float @freeze_fadd(float %input) nounwind {
4+
; GFX11-LABEL: freeze_fadd:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_add_f32_e32 v0, 2.0, v0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
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%x = fadd reassoc nsz arcp contract afn float %input, 1.000000e+00
11+
%y = freeze float %x
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%z = fadd reassoc nsz arcp contract afn float %y, 1.000000e+00
13+
ret float %z
14+
}
15+
16+
define float @freeze_fadd_nnan(float %input) nounwind {
17+
; GFX11-LABEL: freeze_fadd_nnan:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
25+
%x = fadd nnan contract float %input, 1.000000e+00
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%y = freeze float %x
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%z = fadd nnan contract float %y, 1.000000e+00
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ret float %z
29+
}
30+
31+
define <4 x float> @freeze_fadd_vec(<4 x float> %input) nounwind {
32+
; GFX11-LABEL: freeze_fadd_vec:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_dual_add_f32 v0, 0x40a00000, v0 :: v_dual_add_f32 v1, 0x40a00000, v1
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; GFX11-NEXT: v_dual_add_f32 v2, 0x40a00000, v2 :: v_dual_add_f32 v3, 0x40a00000, v3
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
39+
%x = fadd reassoc nsz arcp contract afn <4 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
40+
%y = freeze <4 x float> %x
41+
%z = fadd reassoc nsz arcp contract afn <4 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
42+
ret <4 x float> %z
43+
}
44+
45+
define float @freeze_fsub(float %input) nounwind {
46+
; GFX11-LABEL: freeze_fsub:
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; GFX11: ; %bb.0: ; %entry
48+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
49+
; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
50+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
54+
%x = fsub reassoc nsz arcp contract afn float %input, 1.000000e+00
55+
%y = freeze float %x
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%z = fsub reassoc nsz arcp contract afn float %y, 1.000000e+00
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ret float %z
58+
}
59+
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define float @freeze_fsub_nnan(float %input) nounwind {
61+
; GFX11-LABEL: freeze_fsub_nnan:
62+
; GFX11: ; %bb.0: ; %entry
63+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
66+
; GFX11-NEXT: v_subrev_f32_e32 v0, 1.0, v0
67+
; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
69+
%x = fsub nnan contract float %input, 1.000000e+00
70+
%y = freeze float %x
71+
%z = fsub nnan contract float %y, 1.000000e+00
72+
ret float %z
73+
}
74+
75+
define <4 x float> @freeze_fsub_vec(<4 x float> %input) nounwind {
76+
; GFX11-LABEL: freeze_fsub_vec:
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; GFX11: ; %bb.0: ; %entry
78+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
79+
; GFX11-NEXT: v_dual_add_f32 v0, 0xc0a00000, v0 :: v_dual_add_f32 v1, 0xc0a00000, v1
80+
; GFX11-NEXT: v_dual_add_f32 v2, 0xc0a00000, v2 :: v_dual_add_f32 v3, 0xc0a00000, v3
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; GFX11-NEXT: s_setpc_b64 s[30:31]
82+
entry:
83+
%x = fsub reassoc nsz arcp contract afn <4 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
84+
%y = freeze <4 x float> %x
85+
%z = fsub reassoc nsz arcp contract afn <4 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
86+
ret <4 x float> %z
87+
}
88+
89+
define float @freeze_fmul(float %input) nounwind {
90+
; GFX11-LABEL: freeze_fmul:
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; GFX11: ; %bb.0: ; %entry
92+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_mul_f32_e32 v0, 4.0, v0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
96+
%x = fmul reassoc nsz arcp contract afn float %input, 2.000000e+00
97+
%y = freeze float %x
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%z = fmul reassoc nsz arcp contract afn float %y, 2.000000e+00
99+
ret float %z
100+
}
101+
102+
define float @freeze_fmul_nnan(float %input) nounwind {
103+
; GFX11-LABEL: freeze_fmul_nnan:
104+
; GFX11: ; %bb.0: ; %entry
105+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
106+
; GFX11-NEXT: v_add_f32_e32 v0, v0, v0
107+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
108+
; GFX11-NEXT: v_add_f32_e32 v0, v0, v0
109+
; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
111+
%x = fmul nnan contract float %input, 2.000000e+00
112+
%y = freeze float %x
113+
%z = fmul nnan contract float %y, 2.000000e+00
114+
ret float %z
115+
}
116+
117+
define <8 x float> @freeze_fmul_vec(<8 x float> %input) nounwind {
118+
; GFX11-LABEL: freeze_fmul_vec:
119+
; GFX11: ; %bb.0: ; %entry
120+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
121+
; GFX11-NEXT: v_dual_mul_f32 v0, 4.0, v0 :: v_dual_mul_f32 v1, 0x40c00000, v1
122+
; GFX11-NEXT: v_dual_mul_f32 v2, 0x40c00000, v2 :: v_dual_mul_f32 v3, 4.0, v3
123+
; GFX11-NEXT: v_dual_mul_f32 v4, 4.0, v4 :: v_dual_mul_f32 v5, 0x40c00000, v5
124+
; GFX11-NEXT: v_dual_mul_f32 v6, 0x40c00000, v6 :: v_dual_mul_f32 v7, 4.0, v7
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
127+
%x = fmul reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
128+
%y = freeze <8 x float> %x
129+
%z = fmul reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
130+
ret <8 x float> %z
131+
}
132+
133+
define float @freeze_fdiv(float %input) nounwind {
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; GFX11-LABEL: freeze_fdiv:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_mul_f32_e32 v0, 0x3e800000, v0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
140+
%x = fdiv reassoc nsz arcp contract afn float %input, 2.000000e+00
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%y = freeze float %x
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%z = fdiv reassoc nsz arcp contract afn float %y, 2.000000e+00
143+
ret float %z
144+
}
145+
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define float @freeze_fdiv_nnan(float %input) nounwind {
147+
; GFX11-LABEL: freeze_fdiv_nnan:
148+
; GFX11: ; %bb.0: ; %entry
149+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
150+
; GFX11-NEXT: v_mul_f32_e32 v0, 0.5, v0
151+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
152+
; GFX11-NEXT: v_mul_f32_e32 v0, 0.5, v0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
154+
entry:
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%x = fdiv nnan contract float %input, 2.000000e+00
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%y = freeze float %x
157+
%z = fdiv nnan contract float %y, 2.000000e+00
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ret float %z
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}
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define <8 x float> @freeze_fdiv_vec(<8 x float> %input) nounwind {
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; GFX11-LABEL: freeze_fdiv_vec:
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; GFX11: ; %bb.0: ; %entry
164+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_dual_mul_f32 v3, 0x3e800000, v3 :: v_dual_mul_f32 v4, 0x3e800000, v4
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; GFX11-NEXT: v_dual_mul_f32 v0, 0x3e800000, v0 :: v_dual_mul_f32 v7, 0x3e800000, v7
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; GFX11-NEXT: v_dual_mul_f32 v1, 0x3e2aaaab, v1 :: v_dual_mul_f32 v2, 0x3e2aaaab, v2
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; GFX11-NEXT: v_dual_mul_f32 v5, 0x3e2aaaab, v5 :: v_dual_mul_f32 v6, 0x3e2aaaab, v6
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
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%x = fdiv reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
172+
%y = freeze <8 x float> %x
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%z = fdiv reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
174+
ret <8 x float> %z
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}
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177+
define float @freeze_frem(float %input) nounwind {
178+
; GFX11-LABEL: freeze_frem:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-NEXT: v_trunc_f32_e32 v1, v1
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; GFX11-NEXT: v_fmac_f32_e32 v0, -2.0, v1
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v0
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; GFX11-NEXT: v_trunc_f32_e32 v1, v1
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_fmac_f32_e32 v0, -2.0, v1
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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entry:
192+
%x = frem reassoc nsz arcp contract afn float %input, 2.000000e+00
193+
%y = freeze float %x
194+
%z = frem reassoc nsz arcp contract afn float %y, 2.000000e+00
195+
ret float %z
196+
}
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define float @freeze_frem_nnan(float %input) nounwind {
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; GFX11-LABEL: freeze_frem_nnan:
200+
; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
202+
; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v0
203+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
204+
; GFX11-NEXT: v_trunc_f32_e32 v1, v1
205+
; GFX11-NEXT: v_fma_f32 v1, -2.0, v1, v0
206+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
207+
; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, v0
208+
; GFX11-NEXT: v_mul_f32_e32 v2, 0.5, v1
209+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
210+
; GFX11-NEXT: v_trunc_f32_e32 v2, v2
211+
; GFX11-NEXT: v_fmac_f32_e32 v1, -2.0, v2
212+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
213+
; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v1, v0
214+
; GFX11-NEXT: s_setpc_b64 s[30:31]
215+
entry:
216+
%x = frem nnan contract float %input, 2.000000e+00
217+
%y = freeze float %x
218+
%z = frem nnan contract float %y, 2.000000e+00
219+
ret float %z
220+
}
221+
222+
define <8 x float> @freeze_frem_vec(<8 x float> %input) nounwind {
223+
; GFX11-LABEL: freeze_frem_vec:
224+
; GFX11: ; %bb.0: ; %entry
225+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
226+
; GFX11-NEXT: v_dual_mul_f32 v8, 0x3e800000, v4 :: v_dual_mul_f32 v9, 0x3e800000, v3
227+
; GFX11-NEXT: v_trunc_f32_e32 v11, v0
228+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
229+
; GFX11-NEXT: v_trunc_f32_e32 v8, v8
230+
; GFX11-NEXT: v_trunc_f32_e32 v9, v9
231+
; GFX11-NEXT: v_mul_f32_e32 v10, 0.5, v6
232+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
233+
; GFX11-NEXT: v_dual_sub_f32 v0, v0, v11 :: v_dual_mul_f32 v11, 0x3eaaaaab, v5
234+
; GFX11-NEXT: v_dual_fmac_f32 v4, -4.0, v8 :: v_dual_fmac_f32 v3, -4.0, v9
235+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
236+
; GFX11-NEXT: v_trunc_f32_e32 v10, v10
237+
; GFX11-NEXT: v_trunc_f32_e32 v9, v7
238+
; GFX11-NEXT: v_dual_fmac_f32 v6, -2.0, v10 :: v_dual_sub_f32 v7, v7, v9
239+
; GFX11-NEXT: v_mul_f32_e32 v8, 0.5, v1
240+
; GFX11-NEXT: v_trunc_f32_e32 v9, v11
241+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
242+
; GFX11-NEXT: v_mul_f32_e32 v11, 0x3e800000, v7
243+
; GFX11-NEXT: v_trunc_f32_e32 v8, v8
244+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
245+
; GFX11-NEXT: v_fmac_f32_e32 v1, -2.0, v8
246+
; GFX11-NEXT: v_fmac_f32_e32 v5, 0xc0400000, v9
247+
; GFX11-NEXT: v_mul_f32_e32 v10, 0x3eaaaaab, v2
248+
; GFX11-NEXT: v_mul_f32_e32 v12, 0x3e800000, v0
249+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
250+
; GFX11-NEXT: v_trunc_f32_e32 v8, v10
251+
; GFX11-NEXT: v_trunc_f32_e32 v10, v12
252+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
253+
; GFX11-NEXT: v_fmac_f32_e32 v2, 0xc0400000, v8
254+
; GFX11-NEXT: v_trunc_f32_e32 v8, v11
255+
; GFX11-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v1
256+
; GFX11-NEXT: v_dual_fmac_f32 v0, -4.0, v10 :: v_dual_mul_f32 v11, 0.5, v5
257+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
258+
; GFX11-NEXT: v_fmac_f32_e32 v7, -4.0, v8
259+
; GFX11-NEXT: v_trunc_f32_e32 v9, v12
260+
; GFX11-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v6
261+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
262+
; GFX11-NEXT: v_fmac_f32_e32 v1, 0xc0400000, v9
263+
; GFX11-NEXT: v_trunc_f32_e32 v9, v11
264+
; GFX11-NEXT: v_trunc_f32_e32 v11, v3
265+
; GFX11-NEXT: v_dual_mul_f32 v10, 0.5, v2 :: v_dual_fmac_f32 v5, -2.0, v9
266+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
267+
; GFX11-NEXT: v_sub_f32_e32 v3, v3, v11
268+
; GFX11-NEXT: v_trunc_f32_e32 v8, v10
269+
; GFX11-NEXT: v_trunc_f32_e32 v10, v12
270+
; GFX11-NEXT: v_trunc_f32_e32 v12, v4
271+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
272+
; GFX11-NEXT: v_fmac_f32_e32 v2, -2.0, v8
273+
; GFX11-NEXT: v_fmac_f32_e32 v6, 0xc0400000, v10
274+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
275+
; GFX11-NEXT: v_sub_f32_e32 v4, v4, v12
276+
; GFX11-NEXT: s_setpc_b64 s[30:31]
277+
entry:
278+
%x = frem reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
279+
%y = freeze <8 x float> %x
280+
%z = frem reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
281+
ret <8 x float> %z
282+
}

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