fixup! [AArch64][GlobalISel] Combine Vector Reduction Add Long

Author: chuongg3

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

@@ -1485,8 +1485,7 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
         MIB.buildConstant(LLT::scalar(64), 0)->getOperand(0).getReg();
     Register ExtReg = MIB.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, {ExtTy},
                                      {MidReg, ZeroReg})
-                          ->getOperand(0)
-                          .getReg();
+                          .getReg(0);
 
     if (DstTy.getScalarSizeInBits() < 32)
       MIB.buildTrunc(DstReg, ExtReg);