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[AMDGPU] Auto-generated some lit test patterns (NFC). (#94310)
Also, converted the R600 RUN lines from some tests into standalone tests.
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‎llvm/test/CodeGen/AMDGPU/fabs-r600.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
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; DAGCombiner will transform:
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; (fabsf (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
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; unless isFabsFree returns true
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define amdgpu_kernel void @s_fabsf_fn_free(ptr addrspace(1) %out, i32 %in) {
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; R600-LABEL: s_fabsf_fn_free:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: MOV * T0.W, KC0[2].Z,
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; R600-NEXT: MOV T0.X, |PV.W|,
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; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%bc= bitcast i32 %in to float
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%fabs = call float @fabsf(float %bc)
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store float %fabs, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_fabsf_free(ptr addrspace(1) %out, i32 %in) {
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; R600-LABEL: s_fabsf_free:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: MOV * T0.W, KC0[2].Z,
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; R600-NEXT: MOV T0.X, |PV.W|,
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; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%bc= bitcast i32 %in to float
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%fabs = call float @llvm.fabs.f32(float %bc)
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store float %fabs, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_fabsf_f32(ptr addrspace(1) %out, float %in) {
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; R600-LABEL: s_fabsf_f32:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: MOV * T0.W, KC0[2].Z,
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; R600-NEXT: MOV T0.X, |PV.W|,
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; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%fabs = call float @llvm.fabs.f32(float %in)
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store float %fabs, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @fabs_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
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; R600-LABEL: fabs_v2f32:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: MOV * T0.W, KC0[3].X,
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; R600-NEXT: MOV T0.Y, |PV.W|,
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; R600-NEXT: MOV * T0.W, KC0[2].W,
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; R600-NEXT: MOV T0.X, |PV.W|,
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; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
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store <2 x float> %fabs, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @fabsf_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
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; R600-LABEL: fabsf_v4f32:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: MOV T0.W, KC0[4].X,
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; R600-NEXT: MOV * T1.W, KC0[3].W,
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; R600-NEXT: MOV * T0.W, |PV.W|,
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; R600-NEXT: MOV T0.Z, |T1.W|,
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; R600-NEXT: MOV * T1.W, KC0[3].Z,
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; R600-NEXT: MOV T0.Y, |PV.W|,
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; R600-NEXT: MOV * T1.W, KC0[3].Y,
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; R600-NEXT: MOV T0.X, |PV.W|,
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; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
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store <4 x float> %fabs, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @fabsf_fn_fold(ptr addrspace(1) %out, float %in0, float %in1) {
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; R600-LABEL: fabsf_fn_fold:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
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; R600-NEXT: MUL_IEEE * T1.X, |KC0[2].Z|, KC0[2].W,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%fabs = call float @fabsf(float %in0)
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%fmul = fmul float %fabs, %in1
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store float %fmul, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @fabs_fold(ptr addrspace(1) %out, float %in0, float %in1) {
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; R600-LABEL: fabs_fold:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
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; R600-NEXT: MUL_IEEE * T1.X, |KC0[2].Z|, KC0[2].W,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%fabs = call float @llvm.fabs.f32(float %in0)
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%fmul = fmul float %fabs, %in1
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store float %fmul, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @bitpreserve_fabsf_f32(ptr addrspace(1) %out, float %in) {
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; R600-LABEL: bitpreserve_fabsf_f32:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
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; R600-NEXT: ADD * T1.X, |KC0[2].Z|, 1.0,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%in.bc = bitcast float %in to i32
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%int.abs = and i32 %in.bc, 2147483647
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%bc = bitcast i32 %int.abs to float
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%fadd = fadd float %bc, 1.0
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store float %fadd, ptr addrspace(1) %out
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ret void
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}
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declare float @fabsf(float) readnone
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declare float @llvm.fabs.f32(float) readnone
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declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone
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declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone

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