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AMDGPU: Replace insertelement poison with insertelement undef
This is the bulk update with perl, with cases which require additional update left for later.
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145 files changed

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‎llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -266,7 +266,7 @@ define <4 x float> @v_uitofp_unpack_i32_to_v4f32(i32 %arg0) nounwind {
266266
%mask.lshr.24 = and i32 %lshr.24, 255
267267
%cvt3 = uitofp i32 %mask.lshr.24 to float
268268

269-
%ins.0 = insertelement <4 x float> undef, float %cvt0, i32 0
269+
%ins.0 = insertelement <4 x float> poison, float %cvt0, i32 0
270270
%ins.1 = insertelement <4 x float> %ins.0, float %cvt1, i32 1
271271
%ins.2 = insertelement <4 x float> %ins.1, float %cvt2, i32 2
272272
%ins.3 = insertelement <4 x float> %ins.2, float %cvt3, i32 3

‎llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1061,7 +1061,6 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
10611061
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
10621062
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
10631063
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
1064-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF1]](<3 x s32>)
10651064
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
10661065
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
10671066
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
@@ -1081,7 +1080,7 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
10811080
%load2 = load volatile i32, ptr addrspace(3) undef
10821081
%load3 = load volatile i32, ptr addrspace(3) undef
10831082

1084-
%insert.0 = insertelement <3 x i32> undef, i32 %load0, i32 0
1083+
%insert.0 = insertelement <3 x i32> poison, i32 %load0, i32 0
10851084
%insert.1 = insertelement <3 x i32> %insert.0, i32 %load1, i32 1
10861085
%insert.2 = insertelement <3 x i32> %insert.1, i32 %load2, i32 2
10871086
%insert.3 = insertvalue { <3 x i32>, i32 } poison, <3 x i32> %insert.2, 0
@@ -1097,7 +1096,6 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
10971096
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
10981097
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
10991098
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
1100-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF1]](<3 x s32>)
11011099
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
11021100
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
11031101
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
@@ -1117,7 +1115,7 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
11171115
%load2 = load volatile float, ptr addrspace(3) undef
11181116
%load3 = load volatile i32, ptr addrspace(3) undef
11191117

1120-
%insert.0 = insertelement <3 x float> undef, float %load0, i32 0
1118+
%insert.0 = insertelement <3 x float> poison, float %load0, i32 0
11211119
%insert.1 = insertelement <3 x float> %insert.0, float %load1, i32 1
11221120
%insert.2 = insertelement <3 x float> %insert.1, float %load2, i32 2
11231121
%insert.3 = insertvalue { <3 x float>, i32 } poison, <3 x float> %insert.2, 0

‎llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ bb:
1717
%load = load <2 x i32>, ptr addrspace(3) %gep, align 4
1818
%v1 = extractelement <2 x i32> %load, i32 0
1919
%v2 = extractelement <2 x i32> %load, i32 1
20-
%v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
20+
%v3 = insertelement <2 x i32> poison, i32 %v2, i32 0
2121
%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
2222
store <2 x i32> %v4, ptr addrspace(3) %gep, align 4
2323
ret void
@@ -39,7 +39,7 @@ bb:
3939
%v2 = extractelement <4 x i32> %load, i32 1
4040
%v3 = extractelement <4 x i32> %load, i32 2
4141
%v4 = extractelement <4 x i32> %load, i32 3
42-
%v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
42+
%v5 = insertelement <4 x i32> poison, i32 %v4, i32 0
4343
%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
4444
%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
4545
%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
@@ -62,7 +62,7 @@ bb:
6262
%v1 = extractelement <3 x i32> %load, i32 0
6363
%v2 = extractelement <3 x i32> %load, i32 1
6464
%v3 = extractelement <3 x i32> %load, i32 2
65-
%v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
65+
%v5 = insertelement <3 x i32> poison, i32 %v3, i32 0
6666
%v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
6767
%v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
6868
store <3 x i32> %v7, ptr addrspace(3) %gep, align 4
@@ -79,7 +79,7 @@ bb:
7979
%load = load <2 x i32>, ptr addrspace(3) %gep, align 8
8080
%v1 = extractelement <2 x i32> %load, i32 0
8181
%v2 = extractelement <2 x i32> %load, i32 1
82-
%v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
82+
%v3 = insertelement <2 x i32> poison, i32 %v2, i32 0
8383
%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
8484
store <2 x i32> %v4, ptr addrspace(3) %gep, align 8
8585
ret void
@@ -96,7 +96,7 @@ bb:
9696
%v1 = extractelement <3 x i32> %load, i32 0
9797
%v2 = extractelement <3 x i32> %load, i32 1
9898
%v3 = extractelement <3 x i32> %load, i32 2
99-
%v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
99+
%v5 = insertelement <3 x i32> poison, i32 %v3, i32 0
100100
%v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
101101
%v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
102102
store <3 x i32> %v7, ptr addrspace(3) %gep, align 16
@@ -121,7 +121,7 @@ bb:
121121
%v2 = extractelement <4 x i32> %load, i32 1
122122
%v3 = extractelement <4 x i32> %load, i32 2
123123
%v4 = extractelement <4 x i32> %load, i32 3
124-
%v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
124+
%v5 = insertelement <4 x i32> poison, i32 %v4, i32 0
125125
%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
126126
%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
127127
%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -33,13 +33,13 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_flat(i32 %node_ptr, float
3333
; GCN-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[0:3]
3434
; GCN-NEXT: s_waitcnt vmcnt(0)
3535
; GCN-NEXT: ; return to shader part epilog
36-
%ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0
36+
%ray_origin0 = insertelement <3 x float> poison, float %ray_origin_x, i32 0
3737
%ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1
3838
%ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2
39-
%ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0
39+
%ray_dir0 = insertelement <3 x float> poison, float %ray_dir_x, i32 0
4040
%ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1
4141
%ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2
42-
%ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0
42+
%ray_inv_dir0 = insertelement <3 x float> poison, float %ray_inv_dir_x, i32 0
4343
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
4444
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
4545
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
@@ -96,13 +96,13 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_flat(<2 x i32> %node_ptr
9696
; GCN-NEXT: s_waitcnt vmcnt(0)
9797
; GCN-NEXT: ; return to shader part epilog
9898
%node_ptr = bitcast <2 x i32> %node_ptr_vec to i64
99-
%ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0
99+
%ray_origin0 = insertelement <3 x float> poison, float %ray_origin_x, i32 0
100100
%ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1
101101
%ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2
102-
%ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0
102+
%ray_dir0 = insertelement <3 x float> poison, float %ray_dir_x, i32 0
103103
%ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1
104104
%ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2
105-
%ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0
105+
%ray_inv_dir0 = insertelement <3 x float> poison, float %ray_inv_dir_x, i32 0
106106
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
107107
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
108108
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
@@ -725,13 +725,13 @@ define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr,
725725
%node_ptr = load i32, ptr %gep_node_ptr, align 4
726726
%gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
727727
%ray_extent = load float, ptr %gep_ray, align 4
728-
%ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
728+
%ray_origin0 = insertelement <3 x float> poison, float 0.0, i32 0
729729
%ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
730730
%ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
731-
%ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0
731+
%ray_dir0 = insertelement <3 x float> poison, float 3.0, i32 0
732732
%ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1
733733
%ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2
734-
%ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0
734+
%ray_inv_dir0 = insertelement <3 x float> poison, float 6.0, i32 0
735735
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
736736
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
737737
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
@@ -829,13 +829,13 @@ define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_
829829
%node_ptr = load i32, ptr %gep_node_ptr, align 4
830830
%gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
831831
%ray_extent = load float, ptr %gep_ray, align 4
832-
%ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
832+
%ray_origin0 = insertelement <3 x float> poison, float 0.0, i32 0
833833
%ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
834834
%ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
835-
%ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0
835+
%ray_dir0 = insertelement <3 x half> poison, half 3.0, i32 0
836836
%ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1
837837
%ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
838-
%ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
838+
%ray_inv_dir0 = insertelement <3 x half> poison, half 6.0, i32 0
839839
%ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
840840
%ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
841841
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
@@ -911,13 +911,13 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(ptr %p_ray, <4
911911
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
912912
%gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
913913
%ray_extent = load float, ptr %gep_ray, align 4
914-
%ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
914+
%ray_origin0 = insertelement <3 x float> poison, float 0.0, i32 0
915915
%ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
916916
%ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
917-
%ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0
917+
%ray_dir0 = insertelement <3 x float> poison, float 3.0, i32 0
918918
%ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1
919919
%ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2
920-
%ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0
920+
%ray_inv_dir0 = insertelement <3 x float> poison, float 6.0, i32 0
921921
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
922922
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
923923
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 1111111111111, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
@@ -985,13 +985,13 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(ptr %p_ray
985985
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
986986
%gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
987987
%ray_extent = load float, ptr %gep_ray, align 4
988-
%ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
988+
%ray_origin0 = insertelement <3 x float> poison, float 0.0, i32 0
989989
%ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
990990
%ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
991-
%ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0
991+
%ray_dir0 = insertelement <3 x half> poison, half 3.0, i32 0
992992
%ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1
993993
%ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
994-
%ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
994+
%ray_inv_dir0 = insertelement <3 x half> poison, half 6.0, i32 0
995995
%ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
996996
%ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
997997
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)

‎llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -368,7 +368,7 @@ define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
368368
%elt.1 = extractelement <2 x i32> %cast, i32 1
369369
%res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0)
370370
%res.1 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.1)
371-
%ins.0 = insertelement <2 x i32> undef, i32 %res.0, i32 0
371+
%ins.0 = insertelement <2 x i32> poison, i32 %res.0, i32 0
372372
%ins.1 = insertelement <2 x i32> %ins.0, i32 %res.0, i32 1
373373
%cast.back = bitcast <2 x i32> %ins.1 to i64
374374
ret i64 %cast.back

‎llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -358,7 +358,7 @@ define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
358358
%elt.1 = extractelement <2 x i32> %cast, i32 1
359359
%res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0)
360360
%res.1 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.1)
361-
%ins.0 = insertelement <2 x i32> undef, i32 %res.0, i32 0
361+
%ins.0 = insertelement <2 x i32> poison, i32 %res.0, i32 0
362362
%ins.1 = insertelement <2 x i32> %ins.0, i32 %res.0, i32 1
363363
%cast.back = bitcast <2 x i32> %ins.1 to i64
364364
ret i64 %cast.back

‎llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -355,7 +355,7 @@ define amdgpu_ps i64 @s_udiv_i64(i64 inreg %num, i64 inreg %den) {
355355
%elt.1 = extractelement <2 x i32> %cast, i32 1
356356
%res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0)
357357
%res.1 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.1)
358-
%ins.0 = insertelement <2 x i32> undef, i32 %res.0, i32 0
358+
%ins.0 = insertelement <2 x i32> poison, i32 %res.0, i32 0
359359
%ins.1 = insertelement <2 x i32> %ins.0, i32 %res.0, i32 1
360360
%cast.back = bitcast <2 x i32> %ins.1 to i64
361361
ret i64 %cast.back

‎llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -349,7 +349,7 @@ define amdgpu_ps i64 @s_urem_i64(i64 inreg %num, i64 inreg %den) {
349349
%elt.1 = extractelement <2 x i32> %cast, i32 1
350350
%res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0)
351351
%res.1 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.1)
352-
%ins.0 = insertelement <2 x i32> undef, i32 %res.0, i32 0
352+
%ins.0 = insertelement <2 x i32> poison, i32 %res.0, i32 0
353353
%ins.1 = insertelement <2 x i32> %ins.0, i32 %res.0, i32 1
354354
%cast.back = bitcast <2 x i32> %ins.1 to i64
355355
ret i64 %cast.back

‎llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@ entry:
9090
%xor = xor i32 %a, %b
9191
%r0.val = xor i32 %xor, -1
9292
%r1.val = add i32 %xor, %a
93-
%ins0 = insertelement <2 x i32> undef, i32 %r0.val, i32 0
93+
%ins0 = insertelement <2 x i32> poison, i32 %r0.val, i32 0
9494
%ins1 = insertelement <2 x i32> %ins0, i32 %r1.val, i32 1
9595
ret <2 x i32> %ins1
9696
}
@@ -196,7 +196,7 @@ define amdgpu_ps <2 x i64> @scalar_xnor_i64_mul_use(i64 inreg %a, i64 inreg %b)
196196
%xor = xor i64 %a, %b
197197
%r0.val = xor i64 %xor, -1
198198
%r1.val = add i64 %xor, %a
199-
%ins0 = insertelement <2 x i64> undef, i64 %r0.val, i32 0
199+
%ins0 = insertelement <2 x i64> poison, i64 %r0.val, i32 0
200200
%ins1 = insertelement <2 x i64> %ins0, i64 %r1.val, i32 1
201201
ret <2 x i64> %ins1
202202
}

‎llvm/test/CodeGen/AMDGPU/add3.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -181,7 +181,7 @@ define amdgpu_ps <2 x float> @add3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x
181181
%inner = add i32 %a, %b
182182
%outer = add i32 %inner, %c
183183
%x1 = mul i32 %outer, %x
184-
%r1 = insertelement <2 x i32> undef, i32 %outer, i32 0
184+
%r1 = insertelement <2 x i32> poison, i32 %outer, i32 0
185185
%r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1
186186
%bc = bitcast <2 x i32> %r0 to <2 x float>
187187
ret <2 x float> %bc
@@ -207,7 +207,7 @@ define amdgpu_ps <2 x float> @add3_multiuse_inner(i32 %a, i32 %b, i32 %c) {
207207
; GFX10-NEXT: ; return to shader part epilog
208208
%inner = add i32 %a, %b
209209
%outer = add i32 %inner, %c
210-
%r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
210+
%r1 = insertelement <2 x i32> poison, i32 %inner, i32 0
211211
%r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1
212212
%bc = bitcast <2 x i32> %r0 to <2 x float>
213213
ret <2 x float> %bc

‎llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ define amdgpu_hs void @_amdgpu_hs_main(i32 inreg %arg, i32 inreg %arg1, i32 inre
1717

1818
.beginls: ; preds = %.entry
1919
%tmp15 = extractelement <6 x i32> %arg8, i32 3
20-
%.0.vec.insert.i = insertelement <2 x i32> undef, i32 %tmp15, i32 0
20+
%.0.vec.insert.i = insertelement <2 x i32> poison, i32 %tmp15, i32 0
2121
%.4.vec.insert.i = shufflevector <2 x i32> %.0.vec.insert.i, <2 x i32> undef, <2 x i32> <i32 0, i32 3>
2222
%tmp16 = bitcast <2 x i32> %.4.vec.insert.i to i64
2323
br label %.endls

‎llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ bb:
3636
%tmp21 = getelementptr inbounds <8 x i8>, ptr addrspace(1) %arg, i64 4
3737
%tmp23 = load <16 x i8>, ptr addrspace(1) %tmp21, align 16
3838
%tmp24 = extractelement <16 x i8> %tmp23, i64 3
39-
%tmp1 = insertelement <16 x i8> undef, i8 %tmp3, i32 2
39+
%tmp1 = insertelement <16 x i8> poison, i8 %tmp3, i32 2
4040
%tmp4 = insertelement <16 x i8> %tmp1, i8 0, i32 3
4141
%tmp5 = insertelement <16 x i8> %tmp4, i8 0, i32 4
4242
%tmp7 = insertelement <16 x i8> %tmp5, i8 %tmp6, i32 5

‎llvm/test/CodeGen/AMDGPU/anyext.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -187,7 +187,7 @@ define amdgpu_kernel void @anyext_v2i16_to_v2i32() #0 {
187187
; GFX9-NEXT: s_endpgm
188188
bb:
189189
%tmp = load i16, ptr addrspace(1) undef, align 2
190-
%tmp2 = insertelement <2 x i16> undef, i16 %tmp, i32 1
190+
%tmp2 = insertelement <2 x i16> poison, i16 %tmp, i32 1
191191
%tmp4 = and <2 x i16> %tmp2, <i16 -32767, i16 -32767>
192192
%tmp5 = zext <2 x i16> %tmp4 to <2 x i32>
193193
%tmp6 = shl nuw <2 x i32> %tmp5, <i32 16, i32 16>

‎llvm/test/CodeGen/AMDGPU/bf16-conversions.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -189,7 +189,7 @@ define amdgpu_ps float @fptrunc_f32_f32_to_v2bf16(float %a, float %b) {
189189
entry:
190190
%a.cvt = fptrunc float %a to bfloat
191191
%b.cvt = fptrunc float %b to bfloat
192-
%v2.1 = insertelement <2 x bfloat> undef, bfloat %a.cvt, i32 0
192+
%v2.1 = insertelement <2 x bfloat> poison, bfloat %a.cvt, i32 0
193193
%v2.2 = insertelement <2 x bfloat> %v2.1, bfloat %b.cvt, i32 1
194194
%ret = bitcast <2 x bfloat> %v2.2 to float
195195
ret float %ret
@@ -226,7 +226,7 @@ entry:
226226
%a.cvt = fptrunc float %a.neg to bfloat
227227
%b.abs = call float @llvm.fabs.f32(float %b)
228228
%b.cvt = fptrunc float %b.abs to bfloat
229-
%v2.1 = insertelement <2 x bfloat> undef, bfloat %a.cvt, i32 0
229+
%v2.1 = insertelement <2 x bfloat> poison, bfloat %a.cvt, i32 0
230230
%v2.2 = insertelement <2 x bfloat> %v2.1, bfloat %b.cvt, i32 1
231231
%ret = bitcast <2 x bfloat> %v2.2 to float
232232
ret float %ret

‎llvm/test/CodeGen/AMDGPU/bfi_nested.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -297,7 +297,7 @@ define amdgpu_kernel void @v_bfi_dont_applied_for_scalar_ops(ptr addrspace(1) %o
297297
; GCN-NEXT: s_endpgm
298298
%shift = lshr i32 %b, 16
299299
%tr = trunc i32 %shift to i16
300-
%tmp = insertelement <2 x i16> undef, i16 %a, i32 0
300+
%tmp = insertelement <2 x i16> poison, i16 %a, i32 0
301301
%vec = insertelement <2 x i16> %tmp, i16 %tr, i32 1
302302
%val = bitcast <2 x i16> %vec to i32
303303
store i32 %val, ptr addrspace(1) %out, align 4

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