[MC,test] Improve RISCV/fixups-expr.s

Author: MaskRay

llvm/test/MC/RISCV/fixups-expr.s

@@ -31,19 +31,21 @@ G2:
 .half G2-G1
 .byte .L2-.L1
 .byte G2-G1
-# RELAX: 0x0 R_RISCV_ADD64 .L2 0x0
-# RELAX: 0x0 R_RISCV_SUB64 .L1 0x0
-# RELAX: 0x8 R_RISCV_ADD64 G2 0x0
-# RELAX: 0x8 R_RISCV_SUB64 G1 0x0
-# RELAX: 0x10 R_RISCV_ADD32 .L2 0x0
-# RELAX: 0x10 R_RISCV_SUB32 .L1 0x0
-# RELAX: 0x14 R_RISCV_ADD32 G2 0x0
-# RELAX: 0x14 R_RISCV_SUB32 G1 0x0
-# RELAX: 0x18 R_RISCV_ADD16 .L2 0x0
-# RELAX: 0x18 R_RISCV_SUB16 .L1 0x0
-# RELAX: 0x1A R_RISCV_ADD16 G2 0x0
-# RELAX: 0x1A R_RISCV_SUB16 G1 0x0
-# RELAX: 0x1C R_RISCV_ADD8 .L2 0x0
-# RELAX: 0x1C R_RISCV_SUB8 .L1 0x0
-# RELAX: 0x1D R_RISCV_ADD8 G2 0x0
-# RELAX: 0x1D R_RISCV_SUB8 G1 0x0
+# RELAX:      .rela.data {
+# RELAX-NEXT:   0x0 R_RISCV_ADD64 .L2 0x0
+# RELAX-NEXT:   0x0 R_RISCV_SUB64 .L1 0x0
+# RELAX-NEXT:   0x8 R_RISCV_ADD64 G2 0x0
+# RELAX-NEXT:   0x8 R_RISCV_SUB64 G1 0x0
+# RELAX-NEXT:   0x10 R_RISCV_ADD32 .L2 0x0
+# RELAX-NEXT:   0x10 R_RISCV_SUB32 .L1 0x0
+# RELAX-NEXT:   0x14 R_RISCV_ADD32 G2 0x0
+# RELAX-NEXT:   0x14 R_RISCV_SUB32 G1 0x0
+# RELAX-NEXT:   0x18 R_RISCV_ADD16 .L2 0x0
+# RELAX-NEXT:   0x18 R_RISCV_SUB16 .L1 0x0
+# RELAX-NEXT:   0x1A R_RISCV_ADD16 G2 0x0
+# RELAX-NEXT:   0x1A R_RISCV_SUB16 G1 0x0
+# RELAX-NEXT:   0x1C R_RISCV_ADD8 .L2 0x0
+# RELAX-NEXT:   0x1C R_RISCV_SUB8 .L1 0x0
+# RELAX-NEXT:   0x1D R_RISCV_ADD8 G2 0x0
+# RELAX-NEXT:   0x1D R_RISCV_SUB8 G1 0x0
+# RELAX-NEXT: }