[PhaseOrdering] Add test with removable chained conditions.

Based on https://godbolt.org/z/hTnra7zdY, which is a slightly more
complicated version of the example from
https://discourse.llvm.org/t/why-does-llvm-not-perform-range-analysis-on-integer-values/74341

Author: fhahn

llvm/test/Transforms/PhaseOrdering/runtime-check-removal.ll

@@ -56,3 +56,81 @@ loop.latch:
 exit:
   ret void
 }
+
+
+define void @chained_conditions(i64 noundef %a, i64 noundef %b, i64 noundef %c, i64 noundef %d) #0 {
+; CHECK-LABEL: @chained_conditions(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[A:%.*]], 2048
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ugt i64 [[B:%.*]], 1024
+; CHECK-NEXT:    [[OR_COND:%.*]] = or i1 [[CMP]], [[CMP1]]
+; CHECK-NEXT:    [[CMP3:%.*]] = icmp ugt i64 [[C:%.*]], 1024
+; CHECK-NEXT:    [[OR_COND1:%.*]] = or i1 [[OR_COND]], [[CMP3]]
+; CHECK-NEXT:    br i1 [[OR_COND1]], label [[IF_END10:%.*]], label [[IF_END:%.*]]
+; CHECK:       if.end:
+; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i64 [[B]], [[A]]
+; CHECK-NEXT:    [[ADD4:%.*]] = add nuw nsw i64 [[ADD]], [[C]]
+; CHECK-NEXT:    [[CMP5_NOT:%.*]] = icmp uge i64 [[ADD4]], [[D:%.*]]
+; CHECK-NEXT:    [[CMP8_NOT:%.*]] = icmp ult i64 [[A]], [[D]]
+; CHECK-NEXT:    [[OR_COND7:%.*]] = or i1 [[CMP5_NOT]], [[CMP8_NOT]]
+; CHECK-NEXT:    br i1 [[OR_COND7]], label [[IF_END10]], label [[IF_THEN9:%.*]]
+; CHECK:       if.then9:
+; CHECK-NEXT:    tail call void @bar()
+; CHECK-NEXT:    br label [[IF_END10]]
+; CHECK:       if.end10:
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a.addr = alloca i64, align 8
+  %b.addr = alloca i64, align 8
+  %c.addr = alloca i64, align 8
+  %d.addr = alloca i64, align 8
+  store i64 %a, ptr %a.addr, align 8
+  store i64 %b, ptr %b.addr, align 8
+  store i64 %c, ptr %c.addr, align 8
+  store i64 %d, ptr %d.addr, align 8
+  %0 = load i64, ptr %a.addr, align 8
+  %cmp = icmp ugt i64 %0, 2048
+  br i1 %cmp, label %if.then, label %lor.lhs.false
+
+lor.lhs.false:                                    ; preds = %entry
+  %1 = load i64, ptr %b.addr, align 8
+  %cmp1 = icmp ugt i64 %1, 1024
+  br i1 %cmp1, label %if.then, label %lor.lhs.false2
+
+lor.lhs.false2:                                   ; preds = %lor.lhs.false
+  %2 = load i64, ptr %c.addr, align 8
+  %cmp3 = icmp ugt i64 %2, 1024
+  br i1 %cmp3, label %if.then, label %if.end
+
+if.then:                                          ; preds = %lor.lhs.false2, %lor.lhs.false, %entry
+  br label %if.end10
+
+if.end:                                           ; preds = %lor.lhs.false2
+  %3 = load i64, ptr %a.addr, align 8
+  %4 = load i64, ptr %b.addr, align 8
+  %add = add i64 %3, %4
+  %5 = load i64, ptr %c.addr, align 8
+  %add4 = add i64 %add, %5
+  %6 = load i64, ptr %d.addr, align 8
+  %cmp5 = icmp uge i64 %add4, %6
+  br i1 %cmp5, label %if.then6, label %if.end7
+
+if.then6:                                         ; preds = %if.end
+  br label %if.end10
+
+if.end7:                                          ; preds = %if.end
+  %7 = load i64, ptr %a.addr, align 8
+  %8 = load i64, ptr %d.addr, align 8
+  %cmp8 = icmp uge i64 %7, %8
+  br i1 %cmp8, label %if.then9, label %if.end10
+
+if.then9:                                         ; preds = %if.end7
+  call void @bar()
+  br label %if.end10
+
+if.end10:                                         ; preds = %if.then, %if.then6, %if.then9, %if.end7
+  ret void
+}
+
+declare void @bar()