Address review comments

Author: el-ev

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -15511,25 +15511,21 @@ static SDValue expandMulToNAFSequence(SDNode *N, SelectionDAG &DAG,
   EVT VT = N->getValueType(0);
   const uint64_t BitWidth = VT.getFixedSizeInBits();
 
+  SDValue Result = DAG.getConstant(0, DL, N->getValueType(0));
+  SDValue N0 = N->getOperand(0);
+
   // Find the Non-adjacent form of the multiplier.
-  llvm::SmallVector<std::pair<bool, uint64_t>> Sequence; // {isAdd, shamt}
   for (uint64_t E = MulAmt, I = 0; E && I < BitWidth; ++I, E >>= 1) {
     if (E & 1) {
       bool IsAdd = (E & 3) == 1;
-      Sequence.push_back({IsAdd, I});
       E -= IsAdd ? 1 : -1;
+      SDValue ShiftVal = DAG.getNode(ISD::SHL, DL, VT, N0,
+                                     DAG.getShiftAmountConstant(I, VT, DL));
+      ISD::NodeType AddSubOp = IsAdd ? ISD::ADD : ISD::SUB;
+      Result = DAG.getNode(AddSubOp, DL, VT, Result, ShiftVal);
     }
   }
 
-  SDValue Result = DAG.getConstant(0, DL, N->getValueType(0));
-  SDValue N0 = N->getOperand(0);
-
-  for (const auto &Op : Sequence) {
-    SDValue ShiftVal = DAG.getNode(
-        ISD::SHL, DL, VT, N0, DAG.getShiftAmountConstant(Op.second, VT, DL));
-    ISD::NodeType AddSubOp = Op.first ? ISD::ADD : ISD::SUB;
-    Result = DAG.getNode(AddSubOp, DL, VT, Result, ShiftVal);
-  }
   return Result;
 }
 

llvm/test/CodeGen/RISCV/mul.ll

@@ -955,7 +955,7 @@ define i64 @muli64_p72(i64 %a) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    li a2, 60
+; RV32I-NEXT:    li a2, 72
 ; RV32I-NEXT:    li a3, 0
 ; RV32I-NEXT:    call __muldi3
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
@@ -964,31 +964,31 @@ define i64 @muli64_p72(i64 %a) nounwind {
 ;
 ; RV32IM-LABEL: muli64_p72:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    li a2, 60
-; RV32IM-NEXT:    slli a3, a1, 2
+; RV32IM-NEXT:    li a2, 72
+; RV32IM-NEXT:    slli a3, a1, 3
 ; RV32IM-NEXT:    slli a1, a1, 6
-; RV32IM-NEXT:    sub a1, a1, a3
-; RV32IM-NEXT:    slli a3, a0, 2
+; RV32IM-NEXT:    add a1, a1, a3
+; RV32IM-NEXT:    slli a3, a0, 3
 ; RV32IM-NEXT:    mulhu a2, a0, a2
 ; RV32IM-NEXT:    slli a0, a0, 6
 ; RV32IM-NEXT:    add a1, a2, a1
-; RV32IM-NEXT:    sub a0, a0, a3
+; RV32IM-NEXT:    add a0, a0, a3
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli64_p72:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 2
+; RV64I-NEXT:    slli a1, a0, 3
 ; RV64I-NEXT:    slli a0, a0, 6
-; RV64I-NEXT:    sub a0, a0, a1
+; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: muli64_p72:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    slli a1, a0, 2
+; RV64IM-NEXT:    slli a1, a0, 3
 ; RV64IM-NEXT:    slli a0, a0, 6
-; RV64IM-NEXT:    sub a0, a0, a1
+; RV64IM-NEXT:    add a0, a0, a1
 ; RV64IM-NEXT:    ret
-  %1 = mul i64 %a, 60
+  %1 = mul i64 %a, 72
   ret i64 %1
 }
 
@@ -997,7 +997,7 @@ define i64 @muli64_p68(i64 %a) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT:    li a2, 72
+; RV32I-NEXT:    li a2, 68
 ; RV32I-NEXT:    li a3, 0
 ; RV32I-NEXT:    call __muldi3
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
@@ -1006,11 +1006,11 @@ define i64 @muli64_p68(i64 %a) nounwind {
 ;
 ; RV32IM-LABEL: muli64_p68:
 ; RV32IM:       # %bb.0:
-; RV32IM-NEXT:    li a2, 72
-; RV32IM-NEXT:    slli a3, a1, 3
+; RV32IM-NEXT:    li a2, 68
+; RV32IM-NEXT:    slli a3, a1, 2
 ; RV32IM-NEXT:    slli a1, a1, 6
 ; RV32IM-NEXT:    add a1, a1, a3
-; RV32IM-NEXT:    slli a3, a0, 3
+; RV32IM-NEXT:    slli a3, a0, 2
 ; RV32IM-NEXT:    mulhu a2, a0, a2
 ; RV32IM-NEXT:    slli a0, a0, 6
 ; RV32IM-NEXT:    add a1, a2, a1
@@ -1019,18 +1019,18 @@ define i64 @muli64_p68(i64 %a) nounwind {
 ;
 ; RV64I-LABEL: muli64_p68:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a0, 3
+; RV64I-NEXT:    slli a1, a0, 2
 ; RV64I-NEXT:    slli a0, a0, 6
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: muli64_p68:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    slli a1, a0, 3
+; RV64IM-NEXT:    slli a1, a0, 2
 ; RV64IM-NEXT:    slli a0, a0, 6
 ; RV64IM-NEXT:    add a0, a0, a1
 ; RV64IM-NEXT:    ret
-  %1 = mul i64 %a, 72
+  %1 = mul i64 %a, 68
   ret i64 %1
 }