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Revert "[RISCV] Improve contant materialization to end with 'not' if the cons… (#66950)"
This reverts commit a8b8e94. Forgot to update MC tests.
1 parent a8b8e94 commit ea064ba

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2 files changed

+115
-123
lines changed

2 files changed

+115
-123
lines changed

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

Lines changed: 36 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -171,57 +171,6 @@ static unsigned extractRotateInfo(int64_t Val) {
171171
return 0;
172172
}
173173

174-
static void generateInstSeqLeadingZeros(int64_t Val,
175-
const FeatureBitset &ActiveFeatures,
176-
RISCVMatInt::InstSeq &Res) {
177-
assert(Val > 0 && "Expected postive val");
178-
179-
unsigned LeadingZeros = llvm::countl_zero((uint64_t)Val);
180-
uint64_t ShiftedVal = (uint64_t)Val << LeadingZeros;
181-
// Fill in the bits that will be shifted out with 1s. An example where this
182-
// helps is trailing one masks with 32 or more ones. This will generate
183-
// ADDI -1 and an SRLI.
184-
ShiftedVal |= maskTrailingOnes<uint64_t>(LeadingZeros);
185-
186-
RISCVMatInt::InstSeq TmpSeq;
187-
generateInstSeqImpl(ShiftedVal, ActiveFeatures, TmpSeq);
188-
189-
// Keep the new sequence if it is an improvement or the original is empty.
190-
if ((TmpSeq.size() + 1) < Res.size() ||
191-
(Res.empty() && TmpSeq.size() < 8)) {
192-
TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
193-
Res = TmpSeq;
194-
}
195-
196-
// Some cases can benefit from filling the lower bits with zeros instead.
197-
ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros);
198-
TmpSeq.clear();
199-
generateInstSeqImpl(ShiftedVal, ActiveFeatures, TmpSeq);
200-
201-
// Keep the new sequence if it is an improvement or the original is empty.
202-
if ((TmpSeq.size() + 1) < Res.size() ||
203-
(Res.empty() && TmpSeq.size() < 8)) {
204-
TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
205-
Res = TmpSeq;
206-
}
207-
208-
// If we have exactly 32 leading zeros and Zba, we can try using zext.w at
209-
// the end of the sequence.
210-
if (LeadingZeros == 32 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
211-
// Try replacing upper bits with 1.
212-
uint64_t LeadingOnesVal = Val | maskLeadingOnes<uint64_t>(LeadingZeros);
213-
TmpSeq.clear();
214-
generateInstSeqImpl(LeadingOnesVal, ActiveFeatures, TmpSeq);
215-
216-
// Keep the new sequence if it is an improvement.
217-
if ((TmpSeq.size() + 1) < Res.size() ||
218-
(Res.empty() && TmpSeq.size() < 8)) {
219-
TmpSeq.emplace_back(RISCV::ADD_UW, 0);
220-
Res = TmpSeq;
221-
}
222-
}
223-
}
224-
225174
namespace llvm::RISCVMatInt {
226175
InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
227176
RISCVMatInt::InstSeq Res;
@@ -261,21 +210,47 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
261210
// with no leading zeros and use a final SRLI to restore them.
262211
if (Val > 0) {
263212
assert(Res.size() > 2 && "Expected longer sequence");
264-
generateInstSeqLeadingZeros(Val, ActiveFeatures, Res);
265-
}
213+
unsigned LeadingZeros = llvm::countl_zero((uint64_t)Val);
214+
uint64_t ShiftedVal = (uint64_t)Val << LeadingZeros;
215+
// Fill in the bits that will be shifted out with 1s. An example where this
216+
// helps is trailing one masks with 32 or more ones. This will generate
217+
// ADDI -1 and an SRLI.
218+
ShiftedVal |= maskTrailingOnes<uint64_t>(LeadingZeros);
266219

267-
// If the constant is negative, trying inverting and using our trailing zero
268-
// optimizations. Use an xori to invert the final value.
269-
if (Val < 0 && Res.size() > 3) {
270-
uint64_t InvertedVal = ~(uint64_t)Val;
271220
RISCVMatInt::InstSeq TmpSeq;
272-
generateInstSeqLeadingZeros(InvertedVal, ActiveFeatures, TmpSeq);
221+
generateInstSeqImpl(ShiftedVal, ActiveFeatures, TmpSeq);
273222

274-
// Keep it if we found a sequence that is smaller after inverting.
275-
if (!TmpSeq.empty() && (TmpSeq.size() + 1) < Res.size()) {
276-
TmpSeq.emplace_back(RISCV::XORI, -1);
223+
// Keep the new sequence if it is an improvement.
224+
if ((TmpSeq.size() + 1) < Res.size()) {
225+
TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
226+
Res = TmpSeq;
227+
}
228+
229+
// Some cases can benefit from filling the lower bits with zeros instead.
230+
ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros);
231+
TmpSeq.clear();
232+
generateInstSeqImpl(ShiftedVal, ActiveFeatures, TmpSeq);
233+
234+
// Keep the new sequence if it is an improvement.
235+
if ((TmpSeq.size() + 1) < Res.size()) {
236+
TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
277237
Res = TmpSeq;
278238
}
239+
240+
// If we have exactly 32 leading zeros and Zba, we can try using zext.w at
241+
// the end of the sequence.
242+
if (LeadingZeros == 32 && ActiveFeatures[RISCV::FeatureStdExtZba]) {
243+
// Try replacing upper bits with 1.
244+
uint64_t LeadingOnesVal = Val | maskLeadingOnes<uint64_t>(LeadingZeros);
245+
TmpSeq.clear();
246+
generateInstSeqImpl(LeadingOnesVal, ActiveFeatures, TmpSeq);
247+
248+
// Keep the new sequence if it is an improvement.
249+
if ((TmpSeq.size() + 1) < Res.size()) {
250+
TmpSeq.emplace_back(RISCV::ADD_UW, 0);
251+
Res = TmpSeq;
252+
}
253+
}
279254
}
280255

281256
// If the Low and High halves are the same, use pack. The pack instruction
@@ -454,7 +429,6 @@ OpndKind Inst::getOpndKind() const {
454429
return RISCVMatInt::RegReg;
455430
case RISCV::ADDI:
456431
case RISCV::ADDIW:
457-
case RISCV::XORI:
458432
case RISCV::SLLI:
459433
case RISCV::SRLI:
460434
case RISCV::SLLI_UW:

‎llvm/test/CodeGen/RISCV/imm.ll

Lines changed: 79 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -1058,37 +1058,47 @@ define i64 @imm_end_xori_1() nounwind {
10581058
;
10591059
; RV64I-LABEL: imm_end_xori_1:
10601060
; RV64I: # %bb.0:
1061-
; RV64I-NEXT: lui a0, 983040
1062-
; RV64I-NEXT: srli a0, a0, 3
1063-
; RV64I-NEXT: not a0, a0
1061+
; RV64I-NEXT: li a0, -1
1062+
; RV64I-NEXT: slli a0, a0, 36
1063+
; RV64I-NEXT: addi a0, a0, 1
1064+
; RV64I-NEXT: slli a0, a0, 25
1065+
; RV64I-NEXT: addi a0, a0, -1
10641066
; RV64I-NEXT: ret
10651067
;
10661068
; RV64IZBA-LABEL: imm_end_xori_1:
10671069
; RV64IZBA: # %bb.0:
1068-
; RV64IZBA-NEXT: lui a0, 983040
1069-
; RV64IZBA-NEXT: srli a0, a0, 3
1070-
; RV64IZBA-NEXT: not a0, a0
1070+
; RV64IZBA-NEXT: li a0, -1
1071+
; RV64IZBA-NEXT: slli a0, a0, 36
1072+
; RV64IZBA-NEXT: addi a0, a0, 1
1073+
; RV64IZBA-NEXT: slli a0, a0, 25
1074+
; RV64IZBA-NEXT: addi a0, a0, -1
10711075
; RV64IZBA-NEXT: ret
10721076
;
10731077
; RV64IZBB-LABEL: imm_end_xori_1:
10741078
; RV64IZBB: # %bb.0:
1075-
; RV64IZBB-NEXT: lui a0, 983040
1076-
; RV64IZBB-NEXT: srli a0, a0, 3
1077-
; RV64IZBB-NEXT: not a0, a0
1079+
; RV64IZBB-NEXT: li a0, -1
1080+
; RV64IZBB-NEXT: slli a0, a0, 36
1081+
; RV64IZBB-NEXT: addi a0, a0, 1
1082+
; RV64IZBB-NEXT: slli a0, a0, 25
1083+
; RV64IZBB-NEXT: addi a0, a0, -1
10781084
; RV64IZBB-NEXT: ret
10791085
;
10801086
; RV64IZBS-LABEL: imm_end_xori_1:
10811087
; RV64IZBS: # %bb.0:
1082-
; RV64IZBS-NEXT: lui a0, 983040
1083-
; RV64IZBS-NEXT: srli a0, a0, 3
1084-
; RV64IZBS-NEXT: not a0, a0
1088+
; RV64IZBS-NEXT: li a0, -1
1089+
; RV64IZBS-NEXT: slli a0, a0, 36
1090+
; RV64IZBS-NEXT: addi a0, a0, 1
1091+
; RV64IZBS-NEXT: slli a0, a0, 25
1092+
; RV64IZBS-NEXT: addi a0, a0, -1
10851093
; RV64IZBS-NEXT: ret
10861094
;
10871095
; RV64IXTHEADBB-LABEL: imm_end_xori_1:
10881096
; RV64IXTHEADBB: # %bb.0:
1089-
; RV64IXTHEADBB-NEXT: lui a0, 983040
1090-
; RV64IXTHEADBB-NEXT: srli a0, a0, 3
1091-
; RV64IXTHEADBB-NEXT: not a0, a0
1097+
; RV64IXTHEADBB-NEXT: li a0, -1
1098+
; RV64IXTHEADBB-NEXT: slli a0, a0, 36
1099+
; RV64IXTHEADBB-NEXT: addi a0, a0, 1
1100+
; RV64IXTHEADBB-NEXT: slli a0, a0, 25
1101+
; RV64IXTHEADBB-NEXT: addi a0, a0, -1
10921102
; RV64IXTHEADBB-NEXT: ret
10931103
ret i64 -2305843009180139521 ; 0xE000_0000_01FF_FFFF
10941104
}
@@ -1164,12 +1174,13 @@ define i64 @imm_2reg_1() nounwind {
11641174
;
11651175
; RV64-NOPOOL-LABEL: imm_2reg_1:
11661176
; RV64-NOPOOL: # %bb.0:
1167-
; RV64-NOPOOL-NEXT: lui a0, 1048430
1168-
; RV64-NOPOOL-NEXT: addiw a0, a0, 1493
1177+
; RV64-NOPOOL-NEXT: li a0, -1
1178+
; RV64-NOPOOL-NEXT: slli a0, a0, 35
1179+
; RV64-NOPOOL-NEXT: addi a0, a0, 9
11691180
; RV64-NOPOOL-NEXT: slli a0, a0, 13
1170-
; RV64-NOPOOL-NEXT: addi a0, a0, -1921
1171-
; RV64-NOPOOL-NEXT: srli a0, a0, 4
1172-
; RV64-NOPOOL-NEXT: not a0, a0
1181+
; RV64-NOPOOL-NEXT: addi a0, a0, 837
1182+
; RV64-NOPOOL-NEXT: slli a0, a0, 12
1183+
; RV64-NOPOOL-NEXT: addi a0, a0, 1656
11731184
; RV64-NOPOOL-NEXT: ret
11741185
;
11751186
; RV64I-POOL-LABEL: imm_2reg_1:
@@ -1180,42 +1191,45 @@ define i64 @imm_2reg_1() nounwind {
11801191
;
11811192
; RV64IZBA-LABEL: imm_2reg_1:
11821193
; RV64IZBA: # %bb.0:
1183-
; RV64IZBA-NEXT: lui a0, 1048430
1184-
; RV64IZBA-NEXT: addiw a0, a0, 1493
1194+
; RV64IZBA-NEXT: li a0, -1
1195+
; RV64IZBA-NEXT: slli a0, a0, 35
1196+
; RV64IZBA-NEXT: addi a0, a0, 9
11851197
; RV64IZBA-NEXT: slli a0, a0, 13
1186-
; RV64IZBA-NEXT: addi a0, a0, -1921
1187-
; RV64IZBA-NEXT: srli a0, a0, 4
1188-
; RV64IZBA-NEXT: not a0, a0
1198+
; RV64IZBA-NEXT: addi a0, a0, 837
1199+
; RV64IZBA-NEXT: slli a0, a0, 12
1200+
; RV64IZBA-NEXT: addi a0, a0, 1656
11891201
; RV64IZBA-NEXT: ret
11901202
;
11911203
; RV64IZBB-LABEL: imm_2reg_1:
11921204
; RV64IZBB: # %bb.0:
1193-
; RV64IZBB-NEXT: lui a0, 1048430
1194-
; RV64IZBB-NEXT: addiw a0, a0, 1493
1205+
; RV64IZBB-NEXT: li a0, -1
1206+
; RV64IZBB-NEXT: slli a0, a0, 35
1207+
; RV64IZBB-NEXT: addi a0, a0, 9
11951208
; RV64IZBB-NEXT: slli a0, a0, 13
1196-
; RV64IZBB-NEXT: addi a0, a0, -1921
1197-
; RV64IZBB-NEXT: srli a0, a0, 4
1198-
; RV64IZBB-NEXT: not a0, a0
1209+
; RV64IZBB-NEXT: addi a0, a0, 837
1210+
; RV64IZBB-NEXT: slli a0, a0, 12
1211+
; RV64IZBB-NEXT: addi a0, a0, 1656
11991212
; RV64IZBB-NEXT: ret
12001213
;
12011214
; RV64IZBS-LABEL: imm_2reg_1:
12021215
; RV64IZBS: # %bb.0:
1203-
; RV64IZBS-NEXT: lui a0, 1048430
1204-
; RV64IZBS-NEXT: addiw a0, a0, 1493
1205-
; RV64IZBS-NEXT: slli a0, a0, 13
1206-
; RV64IZBS-NEXT: addi a0, a0, -1921
1207-
; RV64IZBS-NEXT: srli a0, a0, 4
1208-
; RV64IZBS-NEXT: not a0, a0
1216+
; RV64IZBS-NEXT: lui a0, 74565
1217+
; RV64IZBS-NEXT: addiw a0, a0, 1656
1218+
; RV64IZBS-NEXT: bseti a0, a0, 60
1219+
; RV64IZBS-NEXT: bseti a0, a0, 61
1220+
; RV64IZBS-NEXT: bseti a0, a0, 62
1221+
; RV64IZBS-NEXT: bseti a0, a0, 63
12091222
; RV64IZBS-NEXT: ret
12101223
;
12111224
; RV64IXTHEADBB-LABEL: imm_2reg_1:
12121225
; RV64IXTHEADBB: # %bb.0:
1213-
; RV64IXTHEADBB-NEXT: lui a0, 1048430
1214-
; RV64IXTHEADBB-NEXT: addiw a0, a0, 1493
1226+
; RV64IXTHEADBB-NEXT: li a0, -1
1227+
; RV64IXTHEADBB-NEXT: slli a0, a0, 35
1228+
; RV64IXTHEADBB-NEXT: addi a0, a0, 9
12151229
; RV64IXTHEADBB-NEXT: slli a0, a0, 13
1216-
; RV64IXTHEADBB-NEXT: addi a0, a0, -1921
1217-
; RV64IXTHEADBB-NEXT: srli a0, a0, 4
1218-
; RV64IXTHEADBB-NEXT: not a0, a0
1230+
; RV64IXTHEADBB-NEXT: addi a0, a0, 837
1231+
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
1232+
; RV64IXTHEADBB-NEXT: addi a0, a0, 1656
12191233
; RV64IXTHEADBB-NEXT: ret
12201234
ret i64 -1152921504301427080 ; 0xF000_0000_1234_5678
12211235
}
@@ -1710,12 +1724,13 @@ define i64 @imm_neg_9223372034778874949() {
17101724
;
17111725
; RV64-NOPOOL-LABEL: imm_neg_9223372034778874949:
17121726
; RV64-NOPOOL: # %bb.0:
1713-
; RV64-NOPOOL-NEXT: lui a0, 1048329
1714-
; RV64-NOPOOL-NEXT: addiw a0, a0, -1911
1727+
; RV64-NOPOOL-NEXT: li a0, -1
1728+
; RV64-NOPOOL-NEXT: slli a0, a0, 37
1729+
; RV64-NOPOOL-NEXT: addi a0, a0, 31
17151730
; RV64-NOPOOL-NEXT: slli a0, a0, 12
1716-
; RV64-NOPOOL-NEXT: addi a0, a0, -1911
1717-
; RV64-NOPOOL-NEXT: srli a0, a0, 1
1718-
; RV64-NOPOOL-NEXT: not a0, a0
1731+
; RV64-NOPOOL-NEXT: addi a0, a0, -273
1732+
; RV64-NOPOOL-NEXT: slli a0, a0, 14
1733+
; RV64-NOPOOL-NEXT: addi a0, a0, -1093
17191734
; RV64-NOPOOL-NEXT: ret
17201735
;
17211736
; RV64I-POOL-LABEL: imm_neg_9223372034778874949:
@@ -1726,22 +1741,24 @@ define i64 @imm_neg_9223372034778874949() {
17261741
;
17271742
; RV64IZBA-LABEL: imm_neg_9223372034778874949:
17281743
; RV64IZBA: # %bb.0:
1729-
; RV64IZBA-NEXT: lui a0, 1048329
1730-
; RV64IZBA-NEXT: addiw a0, a0, -1911
1744+
; RV64IZBA-NEXT: li a0, -1
1745+
; RV64IZBA-NEXT: slli a0, a0, 37
1746+
; RV64IZBA-NEXT: addi a0, a0, 31
17311747
; RV64IZBA-NEXT: slli a0, a0, 12
1732-
; RV64IZBA-NEXT: addi a0, a0, -1911
1733-
; RV64IZBA-NEXT: srli a0, a0, 1
1734-
; RV64IZBA-NEXT: not a0, a0
1748+
; RV64IZBA-NEXT: addi a0, a0, -273
1749+
; RV64IZBA-NEXT: slli a0, a0, 14
1750+
; RV64IZBA-NEXT: addi a0, a0, -1093
17351751
; RV64IZBA-NEXT: ret
17361752
;
17371753
; RV64IZBB-LABEL: imm_neg_9223372034778874949:
17381754
; RV64IZBB: # %bb.0:
1739-
; RV64IZBB-NEXT: lui a0, 1048329
1740-
; RV64IZBB-NEXT: addiw a0, a0, -1911
1755+
; RV64IZBB-NEXT: li a0, -1
1756+
; RV64IZBB-NEXT: slli a0, a0, 37
1757+
; RV64IZBB-NEXT: addi a0, a0, 31
17411758
; RV64IZBB-NEXT: slli a0, a0, 12
1742-
; RV64IZBB-NEXT: addi a0, a0, -1911
1743-
; RV64IZBB-NEXT: srli a0, a0, 1
1744-
; RV64IZBB-NEXT: not a0, a0
1759+
; RV64IZBB-NEXT: addi a0, a0, -273
1760+
; RV64IZBB-NEXT: slli a0, a0, 14
1761+
; RV64IZBB-NEXT: addi a0, a0, -1093
17451762
; RV64IZBB-NEXT: ret
17461763
;
17471764
; RV64IZBS-LABEL: imm_neg_9223372034778874949:
@@ -1753,12 +1770,13 @@ define i64 @imm_neg_9223372034778874949() {
17531770
;
17541771
; RV64IXTHEADBB-LABEL: imm_neg_9223372034778874949:
17551772
; RV64IXTHEADBB: # %bb.0:
1756-
; RV64IXTHEADBB-NEXT: lui a0, 1048329
1757-
; RV64IXTHEADBB-NEXT: addiw a0, a0, -1911
1773+
; RV64IXTHEADBB-NEXT: li a0, -1
1774+
; RV64IXTHEADBB-NEXT: slli a0, a0, 37
1775+
; RV64IXTHEADBB-NEXT: addi a0, a0, 31
17581776
; RV64IXTHEADBB-NEXT: slli a0, a0, 12
1759-
; RV64IXTHEADBB-NEXT: addi a0, a0, -1911
1760-
; RV64IXTHEADBB-NEXT: srli a0, a0, 1
1761-
; RV64IXTHEADBB-NEXT: not a0, a0
1777+
; RV64IXTHEADBB-NEXT: addi a0, a0, -273
1778+
; RV64IXTHEADBB-NEXT: slli a0, a0, 14
1779+
; RV64IXTHEADBB-NEXT: addi a0, a0, -1093
17621780
; RV64IXTHEADBB-NEXT: ret
17631781
ret i64 -9223372034778874949 ; 0x800000007bbbbbbb
17641782
}

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