Skip to content

Commit ea5fe7c

Browse files
guy-davidguy-david
committed
[AArch64] Verify consecutive vector registers in tbl, tbx
1 parent 57c161a commit ea5fe7c

File tree

4 files changed

+41
-20
lines changed

4 files changed

+41
-20
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -8528,28 +8528,28 @@ multiclass SIMDTableLookup<bit op, string asm> {
85288528

85298529
def : SIMDTableLookupAlias<asm # ".8b",
85308530
!cast<Instruction>(NAME#"v8i8One"),
8531-
V64, VecListOne128>;
8531+
V64, VecListOneConsecutive128>;
85328532
def : SIMDTableLookupAlias<asm # ".8b",
85338533
!cast<Instruction>(NAME#"v8i8Two"),
8534-
V64, VecListTwo128>;
8534+
V64, VecListTwoConsecutive128>;
85358535
def : SIMDTableLookupAlias<asm # ".8b",
85368536
!cast<Instruction>(NAME#"v8i8Three"),
8537-
V64, VecListThree128>;
8537+
V64, VecListThreeConsecutive128>;
85388538
def : SIMDTableLookupAlias<asm # ".8b",
85398539
!cast<Instruction>(NAME#"v8i8Four"),
8540-
V64, VecListFour128>;
8540+
V64, VecListFourConsecutive128>;
85418541
def : SIMDTableLookupAlias<asm # ".16b",
85428542
!cast<Instruction>(NAME#"v16i8One"),
8543-
V128, VecListOne128>;
8543+
V128, VecListOneConsecutive128>;
85448544
def : SIMDTableLookupAlias<asm # ".16b",
85458545
!cast<Instruction>(NAME#"v16i8Two"),
8546-
V128, VecListTwo128>;
8546+
V128, VecListTwoConsecutive128>;
85478547
def : SIMDTableLookupAlias<asm # ".16b",
85488548
!cast<Instruction>(NAME#"v16i8Three"),
8549-
V128, VecListThree128>;
8549+
V128, VecListThreeConsecutive128>;
85508550
def : SIMDTableLookupAlias<asm # ".16b",
85518551
!cast<Instruction>(NAME#"v16i8Four"),
8552-
V128, VecListFour128>;
8552+
V128, VecListFourConsecutive128>;
85538553
}
85548554

85558555
multiclass SIMDTableLookupTied<bit op, string asm> {
@@ -8572,28 +8572,28 @@ multiclass SIMDTableLookupTied<bit op, string asm> {
85728572

85738573
def : SIMDTableLookupAlias<asm # ".8b",
85748574
!cast<Instruction>(NAME#"v8i8One"),
8575-
V64, VecListOne128>;
8575+
V64, VecListOneConsecutive128>;
85768576
def : SIMDTableLookupAlias<asm # ".8b",
85778577
!cast<Instruction>(NAME#"v8i8Two"),
8578-
V64, VecListTwo128>;
8578+
V64, VecListTwoConsecutive128>;
85798579
def : SIMDTableLookupAlias<asm # ".8b",
85808580
!cast<Instruction>(NAME#"v8i8Three"),
8581-
V64, VecListThree128>;
8581+
V64, VecListThreeConsecutive128>;
85828582
def : SIMDTableLookupAlias<asm # ".8b",
85838583
!cast<Instruction>(NAME#"v8i8Four"),
8584-
V64, VecListFour128>;
8584+
V64, VecListFourConsecutive128>;
85858585
def : SIMDTableLookupAlias<asm # ".16b",
85868586
!cast<Instruction>(NAME#"v16i8One"),
8587-
V128, VecListOne128>;
8587+
V128, VecListOneConsecutive128>;
85888588
def : SIMDTableLookupAlias<asm # ".16b",
85898589
!cast<Instruction>(NAME#"v16i8Two"),
8590-
V128, VecListTwo128>;
8590+
V128, VecListTwoConsecutive128>;
85918591
def : SIMDTableLookupAlias<asm # ".16b",
85928592
!cast<Instruction>(NAME#"v16i8Three"),
8593-
V128, VecListThree128>;
8593+
V128, VecListThreeConsecutive128>;
85948594
def : SIMDTableLookupAlias<asm # ".16b",
85958595
!cast<Instruction>(NAME#"v16i8Four"),
8596-
V128, VecListFour128>;
8596+
V128, VecListFourConsecutive128>;
85978597
}
85988598

85998599
//----------------------------------------------------------------------------

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.td

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -646,7 +646,7 @@ class TypedVecListRegOperand<RegisterClass Reg, int lanes, string eltsize>
646646
# eltsize # "'>">;
647647

648648
multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
649-
// With implicit types (probably on instruction instead). E.g. { v0, v1 }
649+
// With implicit types (probably on instruction instead). E.g. { v0, v1 } or {v0, v2, v4}.
650650
def _64AsmOperand : AsmOperandClass {
651651
let Name = NAME # "64";
652652
let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
@@ -667,6 +667,17 @@ multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
667667
let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_128AsmOperand");
668668
}
669669

670+
// With implicit types (probably on instruction instead), consecutive registers. E.g. { v0, v1, v2 }
671+
def _Consecutive128AsmOperand : AsmOperandClass {
672+
let Name = NAME # "Consecutive128";
673+
let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ", true>";
674+
let RenderMethod = "addVectorListOperands<AArch64Operand::VecListIdx_QReg, " # count # ", true>";
675+
}
676+
677+
def "Consecutive128" : RegisterOperand<Reg128, "printImplicitlyTypedVectorList"> {
678+
let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_Consecutive128AsmOperand");
679+
}
680+
670681
// 64-bit register lists with explicit type.
671682

672683
// { v0.8b, v1.8b }

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1445,11 +1445,12 @@ class AArch64Operand : public MCParsedAsmOperand {
14451445

14461446
/// Is this a vector list with the type implicit (presumably attached to the
14471447
/// instruction itself)?
1448-
template <RegKind VectorKind, unsigned NumRegs>
1448+
template <RegKind VectorKind, unsigned NumRegs, bool IsConsecutive = false>
14491449
bool isImplicitlyTypedVectorList() const {
14501450
return Kind == k_VectorList && VectorList.Count == NumRegs &&
14511451
VectorList.NumElements == 0 &&
1452-
VectorList.RegisterKind == VectorKind;
1452+
VectorList.RegisterKind == VectorKind &&
1453+
(!IsConsecutive || (VectorList.Stride == 1));
14531454
}
14541455

14551456
template <RegKind VectorKind, unsigned NumRegs, unsigned NumElements,
@@ -1864,9 +1865,10 @@ class AArch64Operand : public MCParsedAsmOperand {
18641865
VecListIdx_PReg = 3,
18651866
};
18661867

1867-
template <VecListIndexType RegTy, unsigned NumRegs>
1868+
template <VecListIndexType RegTy, unsigned NumRegs, bool IsConsecutive = false>
18681869
void addVectorListOperands(MCInst &Inst, unsigned N) const {
18691870
assert(N == 1 && "Invalid number of operands!");
1871+
assert((!IsConsecutive || (getVectorListStride() == 1)) && "Expected consecutive registers");
18701872
static const unsigned FirstRegs[][5] = {
18711873
/* DReg */ { AArch64::Q0,
18721874
AArch64::D0, AArch64::D0_D1,

‎llvm/test/MC/AArch64/neon-diagnostics.s

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6914,6 +6914,7 @@
69146914
tbl v0.8b, {v1.8b, v2.8b, v3.8b}, v2.8b
69156915
tbl v0.8b, {v1.8b, v2.8b, v3.8b, v4.8b}, v2.8b
69166916
tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b
6917+
tbl.8b v0, {v2, v4, v6, v8}, v10
69176918

69186919
// CHECK-ERROR: error: invalid operand for instruction
69196920
// CHECK-ERROR: tbl v0.8b, {v1.8b}, v2.8b
@@ -6930,12 +6931,16 @@
69306931
// CHECK-ERROR: error: invalid number of vectors
69316932
// CHECK-ERROR: tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b
69326933
// CHECK-ERROR: ^
6934+
// CHECK-ERROR: error: invalid operand for instruction
6935+
// CHECK-ERROR: tbl.8b v0, {v2, v4, v6, v8}, v10
6936+
// CHECK-ERROR: ^
69336937

69346938
tbx v0.8b, {v1.8b}, v2.8b
69356939
tbx v0.8b, {v1.8b, v2.8b}, v2.8b
69366940
tbx v0.8b, {v1.8b, v2.8b, v3.8b}, v2.8b
69376941
tbx v0.8b, {v1.8b, v2.8b, v3.8b, v4.8b}, v2.8b
69386942
tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b
6943+
tbx.8b v0, {v2, v4, v6, v8}, v10
69396944

69406945
// CHECK-ERROR: error: invalid operand for instruction
69416946
// CHECK-ERROR: tbx v0.8b, {v1.8b}, v2.8b
@@ -6952,6 +6957,9 @@
69526957
// CHECK-ERROR: error: invalid number of vectors
69536958
// CHECK-ERROR: tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b
69546959
// CHECK-ERROR: ^
6960+
// CHECK-ERROR: error: invalid operand for instruction
6961+
// CHECK-ERROR: tbx.8b v0, {v2, v4, v6, v8}, v10
6962+
// CHECK-ERROR: ^
69556963

69566964
//----------------------------------------------------------------------
69576965
// Scalar Floating-point Convert To Lower Precision Narrow, Rounding To

0 commit comments

Comments
 (0)