Skip to content

Commit ea75544

Browse files
committed
fix: add Select condition check
1 parent f403016 commit ea75544

File tree

1 file changed

+3
-0
lines changed

1 file changed

+3
-0
lines changed

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13138,6 +13138,9 @@ static SDValue combineVSelectWithAllOnesOrZeros(SDValue Cond, SDValue TVal,
1313813138
}
1313913139
}
1314013140

13141+
assert(DAG.ComputeNumSignBits(Cond) == CondVT.getScalarSizeInBits() &&
13142+
"Select condition no longer all-sign bits");
13143+
1314113144
// select Cond, -1, 0 → bitcast Cond
1314213145
if (IsTAllOne && IsFAllZero)
1314313146
return DAG.getBitcast(VT, Cond);

0 commit comments

Comments
 (0)