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mshockwavea-poduval
mshockwave
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a-poduval
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[XRay][RISCV] RISCV support for XRay (#117368)
Add RISC-V support for XRay. The RV64 implementation has been tested in both QEMU and in our hardware environment. Currently this requires D and C extensions, but since both RV64GC and RVA22/RVA23 are becoming mainstream, I don't think this requirement will be a big problem. Based on the previous work by @a-poduval : https://reviews.llvm.org/D117929 --------- Co-authored-by: Ashwin Poduval <[email protected]>
1 parent 7987f47 commit ea76b2d

15 files changed

+696
-5
lines changed

‎clang/lib/Driver/XRayArgs.cpp

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@@ -51,6 +51,8 @@ XRayArgs::XRayArgs(const ToolChain &TC, const ArgList &Args) {
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case llvm::Triple::mips64:
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case llvm::Triple::mips64el:
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case llvm::Triple::systemz:
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case llvm::Triple::riscv32:
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case llvm::Triple::riscv64:
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break;
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default:
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D.Diag(diag::err_drv_unsupported_opt_for_target)

‎compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake

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@@ -102,7 +102,7 @@ if(APPLE)
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set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM64})
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else()
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set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM32} ${ARM64} ${MIPS32} ${MIPS64}
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powerpc64le ${HEXAGON} ${LOONGARCH64})
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powerpc64le ${HEXAGON} ${LOONGARCH64} ${RISCV32} ${RISCV64})
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endif()
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set(ALL_XRAY_DSO_SUPPORTED_ARCH ${X86_64} ${ARM64})
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set(ALL_SHADOWCALLSTACK_SUPPORTED_ARCH ${ARM64})

‎compiler-rt/lib/xray/CMakeLists.txt

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@@ -96,6 +96,16 @@ set(hexagon_SOURCES
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xray_trampoline_hexagon.S
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)
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set(riscv32_SOURCES
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xray_riscv.cpp
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xray_trampoline_riscv32.S
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)
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set(riscv64_SOURCES
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xray_riscv.cpp
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xray_trampoline_riscv64.S
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)
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set(XRAY_SOURCE_ARCHS
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arm
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armhf
@@ -156,6 +166,8 @@ set(XRAY_ALL_SOURCE_FILES
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${mips64_SOURCES}
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${mips64el_SOURCES}
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${powerpc64le_SOURCES}
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${riscv32_SOURCES}
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${riscv64_SOURCES}
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${XRAY_IMPL_HEADERS}
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)
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list(REMOVE_DUPLICATES XRAY_ALL_SOURCE_FILES)

‎compiler-rt/lib/xray/xray_interface.cpp

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@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64;
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static const int16_t cSledLength = 8;
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#elif defined(__hexagon__)
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static const int16_t cSledLength = 20;
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#elif defined(__riscv) && (__riscv_xlen == 64)
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static const int16_t cSledLength = 68;
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#elif defined(__riscv) && (__riscv_xlen == 32)
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static const int16_t cSledLength = 52;
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#else
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#error "Unsupported CPU Architecture"
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#endif /* CPU architecture */

‎compiler-rt/lib/xray/xray_riscv.cpp

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@@ -0,0 +1,266 @@
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//===-- xray_riscv.cpp ----------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is a part of XRay, a dynamic runtime instrumentation system.
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//
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// Implementation of RISC-V specific routines (32- and 64-bit).
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//
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//===----------------------------------------------------------------------===//
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#include "sanitizer_common/sanitizer_common.h"
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#include "xray_defs.h"
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#include "xray_interface_internal.h"
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#include <atomic>
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namespace __xray {
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// The machine codes for some instructions used in runtime patching.
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enum PatchOpcodes : uint32_t {
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PO_ADDI = 0x00000013, // addi rd, rs1, imm
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PO_ADD = 0x00000033, // add rd, rs1, rs2
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PO_SW = 0x00002023, // sw rs2, imm(rs1)
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PO_SD = 0x00003023, // sd rs2, imm(rs1)
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PO_LUI = 0x00000037, // lui rd, imm
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PO_OR = 0x00006033, // or rd, rs1, rs2
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PO_SLLI = 0x00001013, // slli rd, rs1, shamt
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PO_JALR = 0x00000067, // jalr rd, rs1
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PO_LW = 0x00002003, // lw rd, imm(rs1)
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PO_LD = 0x00003003, // ld rd, imm(rs1)
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PO_J = 0x0000006f, // jal imm
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PO_NOP = PO_ADDI, // addi x0, x0, 0
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};
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enum RegNum : uint32_t {
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RN_X0 = 0,
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RN_RA = 1,
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RN_SP = 2,
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RN_T1 = 6,
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RN_A0 = 10,
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};
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static inline uint32_t encodeRTypeInstruction(uint32_t Opcode, uint32_t Rs1,
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uint32_t Rs2, uint32_t Rd) {
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return Rs2 << 20 | Rs1 << 15 | Rd << 7 | Opcode;
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}
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static inline uint32_t encodeITypeInstruction(uint32_t Opcode, uint32_t Rs1,
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uint32_t Rd, uint32_t Imm) {
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return Imm << 20 | Rs1 << 15 | Rd << 7 | Opcode;
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}
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static inline uint32_t encodeSTypeInstruction(uint32_t Opcode, uint32_t Rs1,
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uint32_t Rs2, uint32_t Imm) {
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uint32_t ImmMSB = (Imm & 0xfe0) << 20;
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uint32_t ImmLSB = (Imm & 0x01f) << 7;
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return ImmMSB | Rs2 << 20 | Rs1 << 15 | ImmLSB | Opcode;
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}
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static inline uint32_t encodeUTypeInstruction(uint32_t Opcode, uint32_t Rd,
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uint32_t Imm) {
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return Imm << 12 | Rd << 7 | Opcode;
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}
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static inline uint32_t encodeJTypeInstruction(uint32_t Opcode, uint32_t Rd,
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uint32_t Imm) {
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uint32_t ImmMSB = (Imm & 0x100000) << 11;
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uint32_t ImmLSB = (Imm & 0x7fe) << 20;
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uint32_t Imm11 = (Imm & 0x800) << 9;
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uint32_t Imm1912 = (Imm & 0xff000);
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return ImmMSB | ImmLSB | Imm11 | Imm1912 | Rd << 7 | Opcode;
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}
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static uint32_t hi20(uint32_t val) { return (val + 0x800) >> 12; }
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static uint32_t lo12(uint32_t val) { return val & 0xfff; }
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static inline bool patchSled(const bool Enable, const uint32_t FuncId,
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const XRaySledEntry &Sled,
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void (*TracingHook)()) XRAY_NEVER_INSTRUMENT {
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// When |Enable| == true,
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// We replace the following compile-time stub (sled):
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//
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// xray_sled_n:
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// J .tmpN
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// 21 or 33 C.NOPs (42 or 66 bytes)
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// .tmpN
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//
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// With one of the following runtime patches:
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//
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// xray_sled_n (32-bit):
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// addi sp, sp, -16 ;create stack frame
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// sw ra, 12(sp) ;save return address
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// sw a0, 8(sp) ;save register a0
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// lui ra, %hi(__xray_FunctionEntry/Exit)
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// addi ra, ra, %lo(__xray_FunctionEntry/Exit)
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// lui a0, %hi(function_id)
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// addi a0, a0, %lo(function_id) ;pass function id
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// jalr ra ;call Tracing hook
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// lw a0, 8(sp) ;restore register a0
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// lw ra, 12(sp) ;restore return address
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// addi sp, sp, 16 ;delete stack frame
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//
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// xray_sled_n (64-bit):
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// addi sp, sp, -32 ;create stack frame
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// sd ra, 24(sp) ;save return address
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// sd a0, 16(sp) ;save register a0
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// sd t1, 8(sp) ;save register t1
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// lui t1, %highest(__xray_FunctionEntry/Exit)
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// addi t1, t1, %higher(__xray_FunctionEntry/Exit)
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// slli t1, t1, 32
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// lui ra, ra, %hi(__xray_FunctionEntry/Exit)
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// addi ra, ra, %lo(__xray_FunctionEntry/Exit)
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// add ra, t1, ra
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// lui a0, %hi(function_id)
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// addi a0, a0, %lo(function_id) ;pass function id
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// jalr ra ;call Tracing hook
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// ld t1, 8(sp) ;restore register t1
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// ld a0, 16(sp) ;restore register a0
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// ld ra, 24(sp) ;restore return address
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// addi sp, sp, 32 ;delete stack frame
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//
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// Replacement of the first 4-byte instruction should be the last and atomic
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// operation, so that the user code which reaches the sled concurrently
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// either jumps over the whole sled, or executes the whole sled when the
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// latter is ready.
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//
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// When |Enable|==false, we set back the first instruction in the sled to be
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// J 44 bytes (rv32)
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// J 68 bytes (rv64)
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uint32_t *Address = reinterpret_cast<uint32_t *>(Sled.address());
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if (Enable) {
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#if __riscv_xlen == 64
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// If the ISA is RV64, the Tracing Hook needs to be typecast to a 64 bit
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// value.
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uint32_t LoTracingHookAddr = lo12(reinterpret_cast<uint64_t>(TracingHook));
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uint32_t HiTracingHookAddr = hi20(reinterpret_cast<uint64_t>(TracingHook));
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uint32_t HigherTracingHookAddr =
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lo12((reinterpret_cast<uint64_t>(TracingHook) + 0x80000000) >> 32);
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uint32_t HighestTracingHookAddr =
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hi20((reinterpret_cast<uint64_t>(TracingHook) + 0x80000000) >> 32);
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#elif __riscv_xlen == 32
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// We typecast the Tracing Hook to a 32 bit value for RV32
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uint32_t LoTracingHookAddr = lo12(reinterpret_cast<uint32_t>(TracingHook));
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uint32_t HiTracingHookAddr = hi20((reinterpret_cast<uint32_t>(TracingHook));
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#endif
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uint32_t LoFunctionID = lo12(FuncId);
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uint32_t HiFunctionID = hi20(FuncId);
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// The sled that is patched in for RISCV64 defined below. We need the entire
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// sleds corresponding to both ISAs to be protected by defines because the
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// first few instructions are all different, because we store doubles in
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// case of RV64 and store words for RV32. Subsequently, we have LUI - and in
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// case of RV64, we need extra instructions from this point on, so we see
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// differences in addresses to which instructions are stored.
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size_t Idx = 1U;
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const uint32_t XLenBytes = __riscv_xlen / 8;
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#if __riscv_xlen == 64
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const uint32_t LoadOp = PatchOpcodes::PO_LD;
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const uint32_t StoreOp = PatchOpcodes::PO_SD;
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#elif __riscv_xlen == 32
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const uint32_t LoadOp = PatchOpcodes::PO_LW;
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const uint32_t StoreOp = PatchOpcodes::PO_SW;
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#endif
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Address[Idx++] = encodeSTypeInstruction(StoreOp, RegNum::RN_SP,
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RegNum::RN_RA, 3 * XLenBytes);
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Address[Idx++] = encodeSTypeInstruction(StoreOp, RegNum::RN_SP,
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RegNum::RN_A0, 2 * XLenBytes);
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#if __riscv_xlen == 64
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Address[Idx++] = encodeSTypeInstruction(StoreOp, RegNum::RN_SP,
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RegNum::RN_T1, XLenBytes);
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Address[Idx++] = encodeUTypeInstruction(PatchOpcodes::PO_LUI, RegNum::RN_T1,
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HighestTracingHookAddr);
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Address[Idx++] =
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encodeITypeInstruction(PatchOpcodes::PO_ADDI, RegNum::RN_T1,
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RegNum::RN_T1, HigherTracingHookAddr);
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Address[Idx++] = encodeITypeInstruction(PatchOpcodes::PO_SLLI,
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RegNum::RN_T1, RegNum::RN_T1, 32);
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#endif
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Address[Idx++] = encodeUTypeInstruction(PatchOpcodes::PO_LUI, RegNum::RN_RA,
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HiTracingHookAddr);
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Address[Idx++] = encodeITypeInstruction(
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PatchOpcodes::PO_ADDI, RegNum::RN_RA, RegNum::RN_RA, LoTracingHookAddr);
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#if __riscv_xlen == 64
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Address[Idx++] = encodeRTypeInstruction(PatchOpcodes::PO_ADD, RegNum::RN_RA,
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RegNum::RN_T1, RegNum::RN_RA);
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#endif
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Address[Idx++] = encodeUTypeInstruction(PatchOpcodes::PO_LUI, RegNum::RN_A0,
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HiFunctionID);
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Address[Idx++] = encodeITypeInstruction(
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PatchOpcodes::PO_ADDI, RegNum::RN_A0, RegNum::RN_A0, LoFunctionID);
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Address[Idx++] = encodeITypeInstruction(PatchOpcodes::PO_JALR,
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RegNum::RN_RA, RegNum::RN_RA, 0);
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#if __riscv_xlen == 64
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Address[Idx++] =
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encodeITypeInstruction(LoadOp, RegNum::RN_SP, RegNum::RN_T1, XLenBytes);
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#endif
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Address[Idx++] = encodeITypeInstruction(LoadOp, RegNum::RN_SP,
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RegNum::RN_A0, 2 * XLenBytes);
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Address[Idx++] = encodeITypeInstruction(LoadOp, RegNum::RN_SP,
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RegNum::RN_RA, 3 * XLenBytes);
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Address[Idx++] = encodeITypeInstruction(
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PatchOpcodes::PO_ADDI, RegNum::RN_SP, RegNum::RN_SP, 4 * XLenBytes);
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uint32_t CreateStackSpace = encodeITypeInstruction(
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PatchOpcodes::PO_ADDI, RegNum::RN_SP, RegNum::RN_SP, -4 * XLenBytes);
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std::atomic_store_explicit(
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reinterpret_cast<std::atomic<uint32_t> *>(Address), CreateStackSpace,
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std::memory_order_release);
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} else {
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uint32_t CreateBranch = encodeJTypeInstruction(
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// Jump distance is different in both ISAs due to difference in size of
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// sleds
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#if __riscv_xlen == 64
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PatchOpcodes::PO_J, RegNum::RN_X0,
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68); // jump encodes an offset of 68
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#elif __riscv_xlen == 32
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PatchOpcodes::PO_J, RegNum::RN_X0,
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44); // jump encodes an offset of 44
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#endif
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std::atomic_store_explicit(
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reinterpret_cast<std::atomic<uint32_t> *>(Address), CreateBranch,
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std::memory_order_release);
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}
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return true;
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}
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bool patchFunctionEntry(const bool Enable, const uint32_t FuncId,
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const XRaySledEntry &Sled,
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const XRayTrampolines &Trampolines,
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bool LogArgs) XRAY_NEVER_INSTRUMENT {
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// We don't support logging argument at this moment, so we always
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// use EntryTrampoline.
240+
return patchSled(Enable, FuncId, Sled, Trampolines.EntryTrampoline);
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}
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bool patchFunctionExit(
244+
const bool Enable, const uint32_t FuncId, const XRaySledEntry &Sled,
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const XRayTrampolines &Trampolines) XRAY_NEVER_INSTRUMENT {
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return patchSled(Enable, FuncId, Sled, Trampolines.ExitTrampoline);
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}
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bool patchFunctionTailExit(
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const bool Enable, const uint32_t FuncId, const XRaySledEntry &Sled,
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const XRayTrampolines &Trampolines) XRAY_NEVER_INSTRUMENT {
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return patchSled(Enable, FuncId, Sled, Trampolines.TailExitTrampoline);
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}
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bool patchCustomEvent(const bool Enable, const uint32_t FuncId,
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const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT {
257+
return false;
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}
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bool patchTypedEvent(const bool Enable, const uint32_t FuncId,
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const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT {
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return false;
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}
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} // namespace __xray
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extern "C" void __xray_ArgLoggerEntry() XRAY_NEVER_INSTRUMENT {}

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