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[AMDGPU] Clear dbg info on CFG intrinsic due to incorrect behaviour in gdb.
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2 files changed

+29
-22
lines changed

2 files changed

+29
-22
lines changed

‎llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -207,6 +207,7 @@ bool SIAnnotateControlFlow::openIf(BranchInst *Term) {
207207
return false;
208208

209209
IRBuilder<> IRB(Term);
210+
IRB.SetCurrentDebugLocation(DebugLoc());
210211
Value *IfCall = IRB.CreateCall(If, {Term->getCondition()});
211212
Value *Cond = IRB.CreateExtractValue(IfCall, {0});
212213
Value *Mask = IRB.CreateExtractValue(IfCall, {1});
@@ -222,6 +223,7 @@ bool SIAnnotateControlFlow::insertElse(BranchInst *Term) {
222223
}
223224

224225
IRBuilder<> IRB(Term);
226+
IRB.SetCurrentDebugLocation(DebugLoc());
225227
Value *ElseCall = IRB.CreateCall(Else, {popSaved()});
226228
Value *Cond = IRB.CreateExtractValue(ElseCall, {0});
227229
Value *Mask = IRB.CreateExtractValue(ElseCall, {1});
@@ -235,7 +237,9 @@ Value *SIAnnotateControlFlow::handleLoopCondition(
235237
Value *Cond, PHINode *Broken, llvm::Loop *L, BranchInst *Term) {
236238

237239
auto CreateBreak = [this, Cond, Broken](Instruction *I) -> CallInst * {
238-
return IRBuilder<>(I).CreateCall(IfBreak, {Cond, Broken});
240+
IRBuilder<> IRB(I);
241+
IRB.SetCurrentDebugLocation(DebugLoc());
242+
return IRB.CreateCall(IfBreak, {Cond, Broken});
239243
};
240244

241245
if (Instruction *Inst = dyn_cast<Instruction>(Cond)) {
@@ -296,7 +300,9 @@ bool SIAnnotateControlFlow::handleLoop(BranchInst *Term) {
296300
Broken->addIncoming(PHIValue, Pred);
297301
}
298302

299-
CallInst *LoopCall = IRBuilder<>(Term).CreateCall(Loop, {Arg});
303+
IRBuilder<> IRB(Term);
304+
IRB.SetCurrentDebugLocation(DebugLoc());
305+
CallInst *LoopCall = IRB.CreateCall(Loop, {Arg});
300306
Term->setCondition(LoopCall);
301307

302308
push(Term->getSuccessor(0), Arg);
@@ -336,8 +342,9 @@ bool SIAnnotateControlFlow::closeControlFlow(BasicBlock *BB) {
336342
// Split edge to make Def dominate Use
337343
FirstInsertionPt = SplitEdge(DefBB, BB, DT, LI)->getFirstInsertionPt();
338344
}
339-
IRBuilder<>(FirstInsertionPt->getParent(), FirstInsertionPt)
340-
.CreateCall(EndCf, {Exec});
345+
IRBuilder<> IRB(FirstInsertionPt->getParent(), FirstInsertionPt);
346+
IRB.SetCurrentDebugLocation(DebugLoc());
347+
IRB.CreateCall(EndCf, {Exec});
341348
}
342349

343350
return true;

‎llvm/test/CodeGen/AMDGPU/si-annotate-dbg-info.ll

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -7,25 +7,25 @@ define amdgpu_ps i32 @if_else(i32 %0) !dbg !5 {
77
; OPT-SAME: i32 [[TMP0:%.*]]) !dbg [[DBG5:![0-9]+]] {
88
; OPT-NEXT: [[C:%.*]] = icmp ne i32 [[TMP0]], 0, !dbg [[DBG13:![0-9]+]]
99
; OPT-NEXT: tail call void @llvm.dbg.value(metadata i1 [[C]], metadata [[META9:![0-9]+]], metadata !DIExpression()), !dbg [[DBG13]]
10-
; OPT-NEXT: [[TMP2:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[C]]), !dbg [[DBG14:![0-9]+]]
11-
; OPT-NEXT: [[TMP3:%.*]] = extractvalue { i1, i64 } [[TMP2]], 0, !dbg [[DBG14]]
12-
; OPT-NEXT: [[TMP4:%.*]] = extractvalue { i1, i64 } [[TMP2]], 1, !dbg [[DBG14]]
13-
; OPT-NEXT: br i1 [[TMP3]], label [[FALSE:%.*]], label [[FLOW:%.*]], !dbg [[DBG14]]
10+
; OPT-NEXT: [[TMP2:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[C]])
11+
; OPT-NEXT: [[TMP3:%.*]] = extractvalue { i1, i64 } [[TMP2]], 0
12+
; OPT-NEXT: [[TMP4:%.*]] = extractvalue { i1, i64 } [[TMP2]], 1
13+
; OPT-NEXT: br i1 [[TMP3]], label [[FALSE:%.*]], label [[FLOW:%.*]], !dbg [[DBG14:![0-9]+]]
1414
; OPT: Flow:
1515
; OPT-NEXT: [[TMP5:%.*]] = phi i32 [ 33, [[FALSE]] ], [ undef, [[TMP1:%.*]] ]
16-
; OPT-NEXT: [[TMP6:%.*]] = call { i1, i64 } @llvm.amdgcn.else.i64.i64(i64 [[TMP4]]), !dbg [[DBG14]]
17-
; OPT-NEXT: [[TMP7:%.*]] = extractvalue { i1, i64 } [[TMP6]], 0, !dbg [[DBG14]]
18-
; OPT-NEXT: [[TMP8:%.*]] = extractvalue { i1, i64 } [[TMP6]], 1, !dbg [[DBG14]]
16+
; OPT-NEXT: [[TMP6:%.*]] = call { i1, i64 } @llvm.amdgcn.else.i64.i64(i64 [[TMP4]])
17+
; OPT-NEXT: [[TMP7:%.*]] = extractvalue { i1, i64 } [[TMP6]], 0
18+
; OPT-NEXT: [[TMP8:%.*]] = extractvalue { i1, i64 } [[TMP6]], 1
1919
; OPT-NEXT: br i1 [[TMP7]], label [[TRUE:%.*]], label [[EXIT:%.*]], !dbg [[DBG14]]
2020
; OPT: true:
2121
; OPT-NEXT: br label [[EXIT]], !dbg [[DBG15:![0-9]+]]
2222
; OPT: false:
2323
; OPT-NEXT: br label [[FLOW]], !dbg [[DBG16:![0-9]+]]
2424
; OPT: exit:
2525
; OPT-NEXT: [[RET:%.*]] = phi i32 [ [[TMP5]], [[FLOW]] ], [ 42, [[TRUE]] ], !dbg [[DBG17:![0-9]+]]
26-
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP8]]), !dbg [[DBG18:![0-9]+]]
26+
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP8]])
2727
; OPT-NEXT: tail call void @llvm.dbg.value(metadata i32 [[RET]], metadata [[META11:![0-9]+]], metadata !DIExpression()), !dbg [[DBG17]]
28-
; OPT-NEXT: ret i32 [[RET]], !dbg [[DBG18]]
28+
; OPT-NEXT: ret i32 [[RET]], !dbg [[DBG18:![0-9]+]]
2929
;
3030
%c = icmp eq i32 %0, 0, !dbg !13
3131
tail call void @llvm.dbg.value(metadata i1 %c, metadata !9, metadata !DIExpression()), !dbg !13
@@ -54,24 +54,24 @@ define amdgpu_ps void @loop_if_break(i32 %n) !dbg !19 {
5454
; OPT-NEXT: tail call void @llvm.dbg.value(metadata i32 [[I]], metadata [[META21:![0-9]+]], metadata !DIExpression()), !dbg [[DBG25]]
5555
; OPT-NEXT: [[C:%.*]] = icmp ugt i32 [[I]], 0, !dbg [[DBG26:![0-9]+]]
5656
; OPT-NEXT: tail call void @llvm.dbg.value(metadata i1 [[C]], metadata [[META22:![0-9]+]], metadata !DIExpression()), !dbg [[DBG26]]
57-
; OPT-NEXT: [[TMP0:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[C]]), !dbg [[DBG27:![0-9]+]]
58-
; OPT-NEXT: [[TMP1:%.*]] = extractvalue { i1, i64 } [[TMP0]], 0, !dbg [[DBG27]]
59-
; OPT-NEXT: [[TMP2:%.*]] = extractvalue { i1, i64 } [[TMP0]], 1, !dbg [[DBG27]]
60-
; OPT-NEXT: br i1 [[TMP1]], label [[LOOP_BODY:%.*]], label [[FLOW]], !dbg [[DBG27]]
57+
; OPT-NEXT: [[TMP0:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[C]])
58+
; OPT-NEXT: [[TMP1:%.*]] = extractvalue { i1, i64 } [[TMP0]], 0
59+
; OPT-NEXT: [[TMP2:%.*]] = extractvalue { i1, i64 } [[TMP0]], 1
60+
; OPT-NEXT: br i1 [[TMP1]], label [[LOOP_BODY:%.*]], label [[FLOW]], !dbg [[DBG27:![0-9]+]]
6161
; OPT: loop_body:
6262
; OPT-NEXT: [[I_NEXT:%.*]] = sub i32 [[I]], 1, !dbg [[DBG28:![0-9]+]]
6363
; OPT-NEXT: tail call void @llvm.dbg.value(metadata i32 [[I_NEXT]], metadata [[META23:![0-9]+]], metadata !DIExpression()), !dbg [[DBG28]]
6464
; OPT-NEXT: br label [[FLOW]], !dbg [[DBG29:![0-9]+]]
6565
; OPT: Flow:
6666
; OPT-NEXT: [[TMP3]] = phi i32 [ [[I_NEXT]], [[LOOP_BODY]] ], [ undef, [[LOOP]] ]
6767
; OPT-NEXT: [[TMP4:%.*]] = phi i1 [ false, [[LOOP_BODY]] ], [ true, [[LOOP]] ]
68-
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]]), !dbg [[DBG27]]
69-
; OPT-NEXT: [[TMP5]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP4]], i64 [[PHI_BROKEN]]), !dbg [[DBG27]]
70-
; OPT-NEXT: [[TMP6:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP5]]), !dbg [[DBG27]]
68+
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]])
69+
; OPT-NEXT: [[TMP5]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP4]], i64 [[PHI_BROKEN]])
70+
; OPT-NEXT: [[TMP6:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP5]])
7171
; OPT-NEXT: br i1 [[TMP6]], label [[EXIT:%.*]], label [[LOOP]], !dbg [[DBG27]]
7272
; OPT: exit:
73-
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP5]]), !dbg [[DBG30:![0-9]+]]
74-
; OPT-NEXT: ret void, !dbg [[DBG30]]
73+
; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP5]])
74+
; OPT-NEXT: ret void, !dbg [[DBG30:![0-9]+]]
7575
;
7676
entry:
7777
br label %loop, !dbg !24

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