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[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
R_RISCV_CALL/R_RISCV_CALL_PLT distinction is not necessary and R_RISCV_CALL has been deprecated. Since https://reviews.llvm.org/D132530 `call foo` assembles to R_RISCV_CALL_PLT. The `@plt` suffix is not useful and can be removed now (matching AArch64 and PowerPC). GNU assembler assembles `call foo` to RISCV_CALL_PLT since 2022-09 (70f35d72ef04cd23771875c1661c9975044a749c). Without this patch, unconditionally changing MO_CALL to MO_PLT could create `jump .L1@plt, a0`, which is invalid in LLVM integrated assembler and GNU assembler.
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‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2035,9 +2035,8 @@ ParseStatus RISCVAsmParser::parseCallSymbol(OperandVector &Operands) {
20352035

20362036
SMLoc E = SMLoc::getFromPointer(S.getPointer() + Identifier.size());
20372037

2038-
RISCVMCExpr::VariantKind Kind = RISCVMCExpr::VK_RISCV_CALL;
2039-
if (Identifier.consume_back("@plt"))
2040-
Kind = RISCVMCExpr::VK_RISCV_CALL_PLT;
2038+
RISCVMCExpr::VariantKind Kind = RISCVMCExpr::VK_RISCV_CALL_PLT;
2039+
(void)Identifier.consume_back("@plt");
20412040

20422041
MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
20432042
Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -41,8 +41,6 @@ void RISCVMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
4141
if (HasVariant)
4242
OS << '%' << getVariantKindName(getKind()) << '(';
4343
Expr->print(OS, MAI);
44-
if (Kind == VK_RISCV_CALL_PLT)
45-
OS << "@plt";
4644
if (HasVariant)
4745
OS << ')';
4846
}

‎llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -167,7 +167,7 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind {
167167
; RV32-NEXT: andi a0, a0, -16
168168
; RV32-NEXT: sub a0, sp, a0
169169
; RV32-NEXT: mv sp, a0
170-
; RV32-NEXT: call notdead@plt
170+
; RV32-NEXT: call notdead
171171
; RV32-NEXT: mv a0, s1
172172
; RV32-NEXT: addi sp, s0, -16
173173
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -204,7 +204,7 @@ define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind {
204204
; RV64-NEXT: andi a0, a0, -16
205205
; RV64-NEXT: sub a0, sp, a0
206206
; RV64-NEXT: mv sp, a0
207-
; RV64-NEXT: call notdead@plt
207+
; RV64-NEXT: call notdead
208208
; RV64-NEXT: mv a0, s1
209209
; RV64-NEXT: addi sp, s0, -32
210210
; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
@@ -229,7 +229,7 @@ define void @va1_caller() nounwind {
229229
; RV32-NEXT: lui a3, 261888
230230
; RV32-NEXT: li a4, 2
231231
; RV32-NEXT: li a2, 0
232-
; RV32-NEXT: call va1@plt
232+
; RV32-NEXT: call va1
233233
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
234234
; RV32-NEXT: addi sp, sp, 16
235235
; RV32-NEXT: ret
@@ -241,7 +241,7 @@ define void @va1_caller() nounwind {
241241
; LP64-NEXT: lui a0, %hi(.LCPI3_0)
242242
; LP64-NEXT: ld a1, %lo(.LCPI3_0)(a0)
243243
; LP64-NEXT: li a2, 2
244-
; LP64-NEXT: call va1@plt
244+
; LP64-NEXT: call va1
245245
; LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
246246
; LP64-NEXT: addi sp, sp, 16
247247
; LP64-NEXT: ret
@@ -255,7 +255,7 @@ define void @va1_caller() nounwind {
255255
; LP64F-NEXT: fmv.d.x fa5, a0
256256
; LP64F-NEXT: li a2, 2
257257
; LP64F-NEXT: fmv.x.d a1, fa5
258-
; LP64F-NEXT: call va1@plt
258+
; LP64F-NEXT: call va1
259259
; LP64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
260260
; LP64F-NEXT: addi sp, sp, 16
261261
; LP64F-NEXT: ret
@@ -269,7 +269,7 @@ define void @va1_caller() nounwind {
269269
; LP64D-NEXT: fmv.d.x fa5, a0
270270
; LP64D-NEXT: li a2, 2
271271
; LP64D-NEXT: fmv.x.d a1, fa5
272-
; LP64D-NEXT: call va1@plt
272+
; LP64D-NEXT: call va1
273273
; LP64D-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
274274
; LP64D-NEXT: addi sp, sp, 16
275275
; LP64D-NEXT: ret
@@ -473,7 +473,7 @@ define void @va2_caller() nounwind {
473473
; RV32-NEXT: addi sp, sp, -16
474474
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
475475
; RV32-NEXT: li a1, 1
476-
; RV32-NEXT: call va2@plt
476+
; RV32-NEXT: call va2
477477
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
478478
; RV32-NEXT: addi sp, sp, 16
479479
; RV32-NEXT: ret
@@ -483,7 +483,7 @@ define void @va2_caller() nounwind {
483483
; RV64-NEXT: addi sp, sp, -16
484484
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
485485
; RV64-NEXT: li a1, 1
486-
; RV64-NEXT: call va2@plt
486+
; RV64-NEXT: call va2
487487
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
488488
; RV64-NEXT: addi sp, sp, 16
489489
; RV64-NEXT: ret
@@ -701,7 +701,7 @@ define void @va3_caller() nounwind {
701701
; RV32-NEXT: li a0, 2
702702
; RV32-NEXT: li a1, 1111
703703
; RV32-NEXT: li a2, 0
704-
; RV32-NEXT: call va3@plt
704+
; RV32-NEXT: call va3
705705
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
706706
; RV32-NEXT: addi sp, sp, 16
707707
; RV32-NEXT: ret
@@ -714,7 +714,7 @@ define void @va3_caller() nounwind {
714714
; RV64-NEXT: addiw a2, a0, -480
715715
; RV64-NEXT: li a0, 2
716716
; RV64-NEXT: li a1, 1111
717-
; RV64-NEXT: call va3@plt
717+
; RV64-NEXT: call va3
718718
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
719719
; RV64-NEXT: addi sp, sp, 16
720720
; RV64-NEXT: ret
@@ -749,7 +749,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind {
749749
; RV32-NEXT: lw s0, 0(a0)
750750
; RV32-NEXT: sw a2, 0(a1)
751751
; RV32-NEXT: lw a0, 0(sp)
752-
; RV32-NEXT: call notdead@plt
752+
; RV32-NEXT: call notdead
753753
; RV32-NEXT: lw a0, 4(sp)
754754
; RV32-NEXT: addi a0, a0, 3
755755
; RV32-NEXT: andi a0, a0, -4
@@ -803,7 +803,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind {
803803
; RV64-NEXT: lwu a1, 0(sp)
804804
; RV64-NEXT: slli a0, a0, 32
805805
; RV64-NEXT: or a0, a0, a1
806-
; RV64-NEXT: call notdead@plt
806+
; RV64-NEXT: call notdead
807807
; RV64-NEXT: ld a0, 8(sp)
808808
; RV64-NEXT: addi a0, a0, 3
809809
; RV64-NEXT: andi a0, a0, -4

‎llvm/test/CodeGen/RISCV/addrspacecast.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ define void @cast1(ptr %ptr) {
2626
; RV32I-NEXT: .cfi_def_cfa_offset 16
2727
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2828
; RV32I-NEXT: .cfi_offset ra, -4
29-
; RV32I-NEXT: call foo@plt
29+
; RV32I-NEXT: call foo
3030
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3131
; RV32I-NEXT: addi sp, sp, 16
3232
; RV32I-NEXT: ret
@@ -37,7 +37,7 @@ define void @cast1(ptr %ptr) {
3737
; RV64I-NEXT: .cfi_def_cfa_offset 16
3838
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
3939
; RV64I-NEXT: .cfi_offset ra, -8
40-
; RV64I-NEXT: call foo@plt
40+
; RV64I-NEXT: call foo
4141
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
4242
; RV64I-NEXT: addi sp, sp, 16
4343
; RV64I-NEXT: ret

‎llvm/test/CodeGen/RISCV/aext-to-sext.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ define void @quux(i32 signext %arg, i32 signext %arg1) nounwind {
1919
; RV64I-NEXT: subw s0, a1, a0
2020
; RV64I-NEXT: .LBB0_2: # %bb2
2121
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
22-
; RV64I-NEXT: call hoge@plt
22+
; RV64I-NEXT: call hoge
2323
; RV64I-NEXT: addiw s0, s0, -1
2424
; RV64I-NEXT: bnez s0, .LBB0_2
2525
; RV64I-NEXT: # %bb.3:

‎llvm/test/CodeGen/RISCV/alloca.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ define void @simple_alloca(i32 %n) nounwind {
1818
; RV32I-NEXT: andi a0, a0, -16
1919
; RV32I-NEXT: sub a0, sp, a0
2020
; RV32I-NEXT: mv sp, a0
21-
; RV32I-NEXT: call notdead@plt
21+
; RV32I-NEXT: call notdead
2222
; RV32I-NEXT: addi sp, s0, -16
2323
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2424
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
@@ -45,7 +45,7 @@ define void @scoped_alloca(i32 %n) nounwind {
4545
; RV32I-NEXT: andi a0, a0, -16
4646
; RV32I-NEXT: sub a0, sp, a0
4747
; RV32I-NEXT: mv sp, a0
48-
; RV32I-NEXT: call notdead@plt
48+
; RV32I-NEXT: call notdead
4949
; RV32I-NEXT: mv sp, s1
5050
; RV32I-NEXT: addi sp, s0, -16
5151
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -91,7 +91,7 @@ define void @alloca_callframe(i32 %n) nounwind {
9191
; RV32I-NEXT: li a6, 7
9292
; RV32I-NEXT: li a7, 8
9393
; RV32I-NEXT: sw t0, 0(sp)
94-
; RV32I-NEXT: call func@plt
94+
; RV32I-NEXT: call func
9595
; RV32I-NEXT: addi sp, sp, 16
9696
; RV32I-NEXT: addi sp, s0, -16
9797
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload

‎llvm/test/CodeGen/RISCV/analyze-branch.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -20,13 +20,13 @@ define void @test_bcc_fallthrough_taken(i32 %in) nounwind {
2020
; RV32I-NEXT: li a1, 42
2121
; RV32I-NEXT: bne a0, a1, .LBB0_3
2222
; RV32I-NEXT: # %bb.1: # %true
23-
; RV32I-NEXT: call test_true@plt
23+
; RV32I-NEXT: call test_true
2424
; RV32I-NEXT: .LBB0_2: # %true
2525
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2626
; RV32I-NEXT: addi sp, sp, 16
2727
; RV32I-NEXT: ret
2828
; RV32I-NEXT: .LBB0_3: # %false
29-
; RV32I-NEXT: call test_false@plt
29+
; RV32I-NEXT: call test_false
3030
; RV32I-NEXT: j .LBB0_2
3131
%tst = icmp eq i32 %in, 42
3232
br i1 %tst, label %true, label %false, !prof !0
@@ -52,13 +52,13 @@ define void @test_bcc_fallthrough_nottaken(i32 %in) nounwind {
5252
; RV32I-NEXT: li a1, 42
5353
; RV32I-NEXT: beq a0, a1, .LBB1_3
5454
; RV32I-NEXT: # %bb.1: # %false
55-
; RV32I-NEXT: call test_false@plt
55+
; RV32I-NEXT: call test_false
5656
; RV32I-NEXT: .LBB1_2: # %true
5757
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
5858
; RV32I-NEXT: addi sp, sp, 16
5959
; RV32I-NEXT: ret
6060
; RV32I-NEXT: .LBB1_3: # %true
61-
; RV32I-NEXT: call test_true@plt
61+
; RV32I-NEXT: call test_true
6262
; RV32I-NEXT: j .LBB1_2
6363
%tst = icmp eq i32 %in, 42
6464
br i1 %tst, label %true, label %false, !prof !1

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