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[GIsel][AArch64] Legalize <2 x i16> for G_INSERT_VECTOR_ELT (#65830)
Widen the vector elements to 64 bits to make sure it legal instead by clamping the number of elements. Depend on D153394. Fixes #63826
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4 files changed

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-18
lines changed

4 files changed

+119
-18
lines changed

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2496,6 +2496,17 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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return Legalized;
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}
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case TargetOpcode::G_INSERT_VECTOR_ELT: {
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if (TypeIdx == 0) {
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Observer.changingInstr(MI);
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const LLT WideEltTy = WideTy.getElementType();
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widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
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widenScalarSrc(MI, WideEltTy, 2, TargetOpcode::G_ANYEXT);
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widenScalarDst(MI, WideTy, 0);
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Observer.changedInstr(MI);
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return Legalized;
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}
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if (TypeIdx == 1) {
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Observer.changingInstr(MI);
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‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -732,8 +732,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
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.legalIf(typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64}))
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.clampMinNumElements(0, s16, 4)
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.clampMaxNumElements(0, s16, 8);
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.widenVectorEltsToVectorMinSize(0, 64);
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getActionDefinitionsBuilder(G_BUILD_VECTOR)
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.legalFor({{v8s8, s8},

‎llvm/test/CodeGen/AArch64/GlobalISel/insert-vector-elt-pr63826.ll

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -o - -verify-machineinstrs -global-isel=1 -global-isel-abort=1 | FileCheck %s --check-prefixes=CHECK
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; RUN: llc < %s -o - -verify-machineinstrs -global-isel=0 | FileCheck %s --check-prefixes=CHECK
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "arm64-apple-ios14.5.0"
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define <2 x i16> @pr63826_v2s16(<2 x i16> %vec) {
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; CHECK-LABEL: pr63826_v2s16:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: mov w8, #1 ; =0x1
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; CHECK-NEXT: mov.s v0[0], w8
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; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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%vec1 = insertelement <2 x i16> %vec, i16 1, i32 0
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ret <2 x i16> %vec1
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}
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define <2 x i8> @pr63826_v2s8(<2 x i8> %vec) {
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; CHECK-LABEL: pr63826_v2s8:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: mov w8, #1 ; =0x1
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; CHECK-NEXT: mov.s v0[0], w8
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; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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%vec1 = insertelement <2 x i8> %vec, i8 1, i32 0
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ret <2 x i8> %vec1
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}
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define <4 x i8> @pr63826_v4s8(<4 x i8> %vec) {
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; CHECK-LABEL: pr63826_v4s8:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: mov w8, #1 ; =0x1
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; CHECK-NEXT: mov.h v0[0], w8
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; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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%vec1 = insertelement <4 x i8> %vec, i8 1, i32 0
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ret <4 x i8> %vec1
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}

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir

Lines changed: 65 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,24 +1,73 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -o - -global-isel-abort=1 | FileCheck %s
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---
4-
name: pr63826
4+
name: pr63826_v2s16
55
body: |
66
bb.0:
7-
; CHECK-LABEL: name: pr63826
8-
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $w0
9-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
10-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
11-
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
12-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[DEF]](s16), [[DEF]](s16)
14-
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[C]](s16), [[C1]](s32)
15-
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[IVEC]](<4 x s16>)
16-
; CHECK-NEXT: $w0 = COPY [[UV2]](<2 x s16>)
17-
%0:_(<2 x s16>) = COPY $w0
18-
%1:_(s16) = G_CONSTANT i16 1
19-
%2:_(s32) = G_CONSTANT i32 42
20-
%4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %0(<2 x s16>), %1(s16), %2(s32)
21-
$w0 = COPY %4(<2 x s16>)
7+
liveins: $d0
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; CHECK-LABEL: name: pr63826_v2s16
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; CHECK: liveins: $d0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s32), [[C]](s32)
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; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $d0
17+
%1:_(<2 x s32>) = COPY $d0
18+
%0:_(<2 x s16>) = G_TRUNC %1(<2 x s32>)
19+
%4:_(s32) = G_CONSTANT i32 0
20+
%3:_(s16) = G_CONSTANT i16 1
21+
%2:_(<2 x s16>) = G_INSERT_VECTOR_ELT %0, %3(s16), %4(s32)
22+
%5:_(<2 x s32>) = G_ANYEXT %2(<2 x s16>)
23+
$d0 = COPY %5(<2 x s32>)
24+
RET_ReallyLR implicit $d0
25+
...
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---
27+
name: pr63826_v2s8
28+
body: |
29+
bb.0:
30+
liveins: $d0
31+
; CHECK-LABEL: name: pr63826_v2s8
32+
; CHECK: liveins: $d0
33+
; CHECK-NEXT: {{ $}}
34+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
35+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
36+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
37+
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s32), [[C]](s32)
38+
; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $d0
40+
%1:_(<2 x s32>) = COPY $d0
41+
%0:_(<2 x s8>) = G_TRUNC %1(<2 x s32>)
42+
%4:_(s32) = G_CONSTANT i32 0
43+
%3:_(s8) = G_CONSTANT i8 1
44+
%2:_(<2 x s8>) = G_INSERT_VECTOR_ELT %0, %3(s8), %4(s32)
45+
%5:_(<2 x s32>) = G_ANYEXT %2(<2 x s8>)
46+
$d0 = COPY %5(<2 x s32>)
47+
RET_ReallyLR implicit $d0
48+
...
49+
---
50+
name: pr63826_v4s8
51+
body: |
52+
bb.0:
53+
liveins: $d0
54+
; CHECK-LABEL: name: pr63826_v4s8
55+
; CHECK: liveins: $d0
56+
; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
59+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
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; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s16), [[C]](s32)
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; CHECK-NEXT: $d0 = COPY [[IVEC]](<4 x s16>)
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%1:_(<4 x s16>) = COPY $d0
64+
%0:_(<4 x s8>) = G_TRUNC %1(<4 x s16>)
65+
%4:_(s32) = G_CONSTANT i32 0
66+
%3:_(s8) = G_CONSTANT i8 1
67+
%2:_(<4 x s8>) = G_INSERT_VECTOR_ELT %0, %3(s8), %4(s32)
68+
%5:_(<4 x s16>) = G_ANYEXT %2(<4 x s8>)
69+
$d0 = COPY %5(<4 x s16>)
70+
RET_ReallyLR implicit $d0
2271
...
2372
---
2473
name: v8s8

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