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Jinsong Ji
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[PowerPC] Add XL Compat fetch builtins
Prototype ``` unsigned int __fetch_and_add (volatile unsigned int* addr, unsigned int val); unsigned long __fetch_and_addlp (volatile unsigned long* addr, unsigned long val); ``` Ref: https://www.ibm.com/docs/en/xl-c-and-cpp-linux/16.1.1?topic=functions-fetch Reviewed By: #powerpc, w2yehia, lkail Differential Revision: https://reviews.llvm.org/D104991
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‎clang/include/clang/Basic/BuiltinsPPC.def

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@@ -47,6 +47,14 @@ BUILTIN(__builtin_ppc_dcbz, "vv*", "")
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BUILTIN(__builtin_ppc_icbt, "vv*", "")
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BUILTIN(__builtin_ppc_compare_and_swap, "iiD*i*i", "")
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BUILTIN(__builtin_ppc_compare_and_swaplp, "iLiD*Li*Li", "")
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BUILTIN(__builtin_ppc_fetch_and_add, "UiUiD*Ui", "")
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BUILTIN(__builtin_ppc_fetch_and_addlp, "ULiULiD*ULi", "")
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BUILTIN(__builtin_ppc_fetch_and_and, "UiUiD*Ui", "")
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BUILTIN(__builtin_ppc_fetch_and_andlp, "ULiULiD*ULi", "")
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BUILTIN(__builtin_ppc_fetch_and_or, "UiUiD*Ui", "")
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BUILTIN(__builtin_ppc_fetch_and_orlp, "ULiULiD*ULi", "")
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BUILTIN(__builtin_ppc_fetch_and_swap, "UiUiD*Ui", "")
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BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
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BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
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‎clang/lib/Basic/Targets/PPC.cpp

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@@ -100,6 +100,14 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
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Builder.defineMacro("__compare_and_swap", "__builtin_ppc_compare_and_swap");
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Builder.defineMacro("__compare_and_swaplp",
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"__builtin_ppc_compare_and_swaplp");
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Builder.defineMacro("__fetch_and_add", "__builtin_ppc_fetch_and_add");
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Builder.defineMacro("__fetch_and_addlp", "__builtin_ppc_fetch_and_addlp");
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Builder.defineMacro("__fetch_and_and", "__builtin_ppc_fetch_and_and");
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Builder.defineMacro("__fetch_and_andlp", "__builtin_ppc_fetch_and_andlp");
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Builder.defineMacro("__fetch_and_or", "__builtin_ppc_fetch_and_or");
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Builder.defineMacro("__fetch_and_orlp", "__builtin_ppc_fetch_and_orlp");
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Builder.defineMacro("__fetch_and_swap", "__builtin_ppc_fetch_and_swap");
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Builder.defineMacro("__fetch_and_swaplp", "__builtin_ppc_fetch_and_swaplp");
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}
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/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

‎clang/lib/CodeGen/CGBuiltin.cpp

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@@ -15440,6 +15440,27 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID,
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llvm::AtomicOrdering::Monotonic, llvm::AtomicOrdering::Monotonic, true);
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return Pair.second;
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}
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case PPC::BI__builtin_ppc_fetch_and_add:
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case PPC::BI__builtin_ppc_fetch_and_addlp: {
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return MakeBinaryAtomicValue(*this, AtomicRMWInst::Add, E,
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llvm::AtomicOrdering::Monotonic);
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}
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case PPC::BI__builtin_ppc_fetch_and_and:
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case PPC::BI__builtin_ppc_fetch_and_andlp: {
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return MakeBinaryAtomicValue(*this, AtomicRMWInst::And, E,
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llvm::AtomicOrdering::Monotonic);
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}
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case PPC::BI__builtin_ppc_fetch_and_or:
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case PPC::BI__builtin_ppc_fetch_and_orlp: {
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return MakeBinaryAtomicValue(*this, AtomicRMWInst::Or, E,
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llvm::AtomicOrdering::Monotonic);
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}
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case PPC::BI__builtin_ppc_fetch_and_swap:
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case PPC::BI__builtin_ppc_fetch_and_swaplp: {
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return MakeBinaryAtomicValue(*this, AtomicRMWInst::Xchg, E,
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llvm::AtomicOrdering::Monotonic);
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}
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}
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}
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‎clang/test/CodeGen/builtins-ppc-xlcompat-fetch-error.c

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// REQUIRES: powerpc-registered-target
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// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-cpu pwr8 \
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// RUN: -verify %s
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void test_builtin_ppc_fetch_and_add2() {
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volatile int a = 0;
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unsigned int b = 0;
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__fetch_and_add(&a, b); // expected-warning {{passing 'volatile int *' to parameter of type 'volatile unsigned int *' converts between pointers to integer types with different sign}}
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}
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void test_builtin_ppc_fetch_and_addlp() {
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volatile long a = 0;
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unsigned long b = 0;
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__fetch_and_addlp(&a, b); // expected-warning {{passing 'volatile long *' to parameter of type 'volatile unsigned long *' converts between pointers to integer types with different sign}}
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}

‎clang/test/CodeGen/builtins-ppc-xlcompat-fetch.c

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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// REQUIRES: powerpc-registered-target
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// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
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// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
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// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
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// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
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// CHECK-LABEL: @test_builtin_ppc_fetch_and_add(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
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// CHECK-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw add i32* [[A_ADDR]], i32 [[TMP1]] monotonic, align 4
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// CHECK-NEXT: ret void
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//
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void test_builtin_ppc_fetch_and_add(unsigned int a, unsigned int b) {
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__fetch_and_add(&a, b);
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}
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// CHECK-LABEL: @test_builtin_ppc_fetch_and_addlp(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
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// CHECK-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw add i64* [[A_ADDR]], i64 [[TMP1]] monotonic, align 8
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// CHECK-NEXT: ret void
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//
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void test_builtin_ppc_fetch_and_addlp(unsigned long a, unsigned long b) {
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__fetch_and_addlp(&a, b);
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}
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// CHECK-LABEL: @test_builtin_ppc_fetch_and_and(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
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// CHECK-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw and i32* [[A_ADDR]], i32 [[TMP1]] monotonic, align 4
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// CHECK-NEXT: ret void
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//
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void test_builtin_ppc_fetch_and_and(unsigned int a, unsigned int b) {
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__fetch_and_and(&a, b);
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}
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// CHECK-LABEL: @test_builtin_ppc_fetch_and_andlp(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
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// CHECK-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw and i64* [[A_ADDR]], i64 [[TMP1]] monotonic, align 8
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// CHECK-NEXT: ret void
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//
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void test_builtin_ppc_fetch_and_andlp(unsigned long a, unsigned long b) {
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__fetch_and_andlp(&a, b);
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}
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// CHECK-LABEL: @test_builtin_ppc_fetch_and_or(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
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// CHECK-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw or i32* [[A_ADDR]], i32 [[TMP1]] monotonic, align 4
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// CHECK-NEXT: ret void
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//
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void test_builtin_ppc_fetch_and_or(unsigned int a, unsigned int b) {
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__fetch_and_or(&a, b);
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}
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// CHECK-LABEL: @test_builtin_ppc_fetch_and_orlp(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
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// CHECK-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw or i64* [[A_ADDR]], i64 [[TMP1]] monotonic, align 8
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// CHECK-NEXT: ret void
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//
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void test_builtin_ppc_fetch_and_orlp(unsigned long a, unsigned long b) {
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__fetch_and_orlp(&a, b);
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}
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// CHECK-LABEL: @test_builtin_ppc_fetch_and_swap(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
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// CHECK-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw xchg i32* [[A_ADDR]], i32 [[TMP1]] monotonic, align 4
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// CHECK-NEXT: ret void
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//
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void test_builtin_ppc_fetch_and_swap(unsigned int a, unsigned int b) {
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__fetch_and_swap(&a, b);
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}
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// CHECK-LABEL: @test_builtin_ppc_fetch_and_swaplp(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
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// CHECK-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw xchg i64* [[A_ADDR]], i64 [[TMP1]] monotonic, align 8
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// CHECK-NEXT: ret void
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//
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void test_builtin_ppc_fetch_and_swaplp(unsigned long a, unsigned long b) {
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__fetch_and_swaplp(&a, b);
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}

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