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Reapply "SystemZ: Fold copy of vector immediate to gr128" (#91099)
This reverts commit a415b4d. Modify the instruction in place to transform it into a REG_SEQUENCE, which is what other implementations of foldImmediate do. Also start erasing the def instruction if there are no other uses. Fixes #91110.
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‎llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

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Original file line numberDiff line numberDiff line change
@@ -640,6 +640,48 @@ bool SystemZInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
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Register Reg,
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MachineRegisterInfo *MRI) const {
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unsigned DefOpc = DefMI.getOpcode();
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if (DefOpc == SystemZ::VGBM) {
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int64_t ImmVal = DefMI.getOperand(1).getImm();
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if (ImmVal != 0) // TODO: Handle other values
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return false;
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// Fold gr128 = COPY (vr128 VGBM imm)
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//
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// %tmp:gr64 = LGHI 0
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// to gr128 = REG_SEQUENCE %tmp, %tmp
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assert(DefMI.getOperand(0).getReg() == Reg);
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if (!UseMI.isCopy())
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return false;
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Register CopyDstReg = UseMI.getOperand(0).getReg();
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if (CopyDstReg.isVirtual() &&
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MRI->getRegClass(CopyDstReg) == &SystemZ::GR128BitRegClass &&
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MRI->hasOneNonDBGUse(Reg)) {
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// TODO: Handle physical registers
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// TODO: Handle gr64 uses with subregister indexes
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// TODO: Should this multi-use cases?
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Register TmpReg = MRI->createVirtualRegister(&SystemZ::GR64BitRegClass);
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MachineBasicBlock &MBB = *UseMI.getParent();
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loadImmediate(MBB, UseMI.getIterator(), TmpReg, ImmVal);
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UseMI.setDesc(get(SystemZ::REG_SEQUENCE));
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UseMI.getOperand(1).setReg(TmpReg);
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MachineInstrBuilder(*MBB.getParent(), &UseMI)
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.addImm(SystemZ::subreg_h64)
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.addReg(TmpReg)
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.addImm(SystemZ::subreg_l64);
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if (MRI->use_nodbg_empty(Reg))
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DefMI.eraseFromParent();
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return true;
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}
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return false;
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}
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if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
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DefOpc != SystemZ::LGHI)
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return false;
@@ -2237,3 +2279,16 @@ areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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return false;
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}
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bool SystemZInstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
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const Register Reg,
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int64_t &ImmVal) const {
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if (MI.getOpcode() == SystemZ::VGBM && Reg == MI.getOperand(0).getReg()) {
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ImmVal = MI.getOperand(1).getImm();
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// TODO: Handle non-0 values
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return ImmVal == 0;
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}
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return false;
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}

‎llvm/lib/Target/SystemZ/SystemZInstrInfo.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -383,6 +383,9 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
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bool
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areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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const MachineInstr &MIb) const override;
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bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg,
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int64_t &ImmVal) const override;
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};
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} // end namespace llvm

‎llvm/test/CodeGen/SystemZ/fold-copy-vector-immediate.mir

Lines changed: 206 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,206 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
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# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -run-pass=peephole-opt -o - %s | FileCheck %s
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---
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name: fold_vgbm_0_copyvr128_to_gr128_virtreg
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r2d
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; CHECK-LABEL: name: fold_vgbm_0_copyvr128_to_gr128_virtreg
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; CHECK: liveins: $r2d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
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; CHECK-NEXT: [[LGHI:%[0-9]+]]:gr64bit = LGHI 0
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:gr128bit = REG_SEQUENCE [[LGHI]], %subreg.subreg_h64, [[LGHI]], %subreg.subreg_l64
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; CHECK-NEXT: $r0q = COPY [[REG_SEQUENCE]]
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; CHECK-NEXT: Return implicit $r0q
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%0:gr64bit = COPY $r2d
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%1:addr64bit = COPY %0
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%2:vr128bit = VGBM 0
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%3:gr128bit = COPY %2
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$r0q = COPY %3
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Return implicit $r0q
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...
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---
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name: fold_vgbm_0_copyvr128_to_gr128_virtreg_dbg_use
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r2d
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; CHECK-LABEL: name: fold_vgbm_0_copyvr128_to_gr128_virtreg_dbg_use
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; CHECK: liveins: $r2d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
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; CHECK-NEXT: [[LGHI:%[0-9]+]]:gr64bit = LGHI 0
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:gr128bit = REG_SEQUENCE [[LGHI]], %subreg.subreg_h64, [[LGHI]], %subreg.subreg_l64
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; CHECK-NEXT: DBG_VALUE %2:vr128bit
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; CHECK-NEXT: $r0q = COPY [[REG_SEQUENCE]]
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; CHECK-NEXT: Return implicit $r0q
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%0:gr64bit = COPY $r2d
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%1:addr64bit = COPY %0
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%2:vr128bit = VGBM 0
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%3:gr128bit = COPY %2
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DBG_VALUE %2
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$r0q = COPY %3
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Return implicit $r0q
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...
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---
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name: fold_vgbm_0_copyvr128_to_gr128_virtreg_multi_use
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r2d
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; CHECK-LABEL: name: fold_vgbm_0_copyvr128_to_gr128_virtreg_multi_use
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; CHECK: liveins: $r2d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
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; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr128bit = COPY [[VGBM]]
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; CHECK-NEXT: $r0q = COPY [[COPY2]]
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; CHECK-NEXT: $r2q = COPY [[COPY2]]
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; CHECK-NEXT: Return implicit $r0q, implicit $r2q
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%0:gr64bit = COPY $r2d
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%1:addr64bit = COPY %0
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%2:vr128bit = VGBM 0
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%3:gr128bit = COPY %2
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%4:gr128bit = COPY %2
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$r0q = COPY %3
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$r2q = COPY %4
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Return implicit $r0q, implicit $r2q
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...
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---
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name: fold_vgbm_0_copyvr128_to_gr128_physreg
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r2d
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; CHECK-LABEL: name: fold_vgbm_0_copyvr128_to_gr128_physreg
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; CHECK: liveins: $r2d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
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; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 0
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; CHECK-NEXT: $r0q = COPY [[VGBM]]
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; CHECK-NEXT: Return implicit $r0q
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%0:gr64bit = COPY $r2d
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%1:addr64bit = COPY %0
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%2:vr128bit = VGBM 0
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$r0q = COPY %2
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Return implicit $r0q
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...
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---
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name: no_fold_vgbm_0_copyvr128_to_vr128_virtreg
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r2d
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; CHECK-LABEL: name: no_fold_vgbm_0_copyvr128_to_vr128_virtreg
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; CHECK: liveins: $r2d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
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; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr128bit = COPY [[VGBM]]
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; CHECK-NEXT: $v0 = COPY [[COPY2]]
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; CHECK-NEXT: Return implicit $v0
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%0:gr64bit = COPY $r2d
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%1:addr64bit = COPY %0
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%2:vr128bit = VGBM 0
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%3:vr128bit = COPY %2
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$v0 = COPY %3
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Return implicit $v0
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...
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---
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name: no_fold_vgbm_0_copyvr128_to_vr128_physreg
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r2d
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; CHECK-LABEL: name: no_fold_vgbm_0_copyvr128_to_vr128_physreg
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; CHECK: liveins: $r2d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
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; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 0
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; CHECK-NEXT: $v0 = COPY [[VGBM]]
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; CHECK-NEXT: Return implicit $v0
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%0:gr64bit = COPY $r2d
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%1:addr64bit = COPY %0
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%2:vr128bit = VGBM 0
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$v0 = COPY %2
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Return implicit $v0
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...
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---
144+
name: fold_vgbm_1_copyvr128_to_gr128_virtreg
145+
tracksRegLiveness: true
146+
body: |
147+
bb.0:
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liveins: $r2d
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; CHECK-LABEL: name: fold_vgbm_1_copyvr128_to_gr128_virtreg
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; CHECK: liveins: $r2d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
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; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr128bit = COPY [[VGBM]]
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; CHECK-NEXT: $r0q = COPY [[COPY2]]
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; CHECK-NEXT: Return implicit $r0q
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%0:gr64bit = COPY $r2d
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%1:addr64bit = COPY %0
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%2:vr128bit = VGBM 1
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%3:gr128bit = COPY %2
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$r0q = COPY %3
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Return implicit $r0q
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...
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---
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name: no_fold_vgbm_0_noncopy_use
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r2d
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; CHECK-LABEL: name: no_fold_vgbm_0_noncopy_use
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; CHECK: liveins: $r2d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
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; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 0
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; CHECK-NEXT: Return implicit [[VGBM]]
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%0:gr64bit = COPY $r2d
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%1:addr64bit = COPY %0
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%2:vr128bit = VGBM 0
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Return implicit %2
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...
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---
186+
name: fold_vgbm_0_copyvr128_to_gr64_subreg_h64
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r2d
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; CHECK-LABEL: name: fold_vgbm_0_copyvr128_to_gr64_subreg_h64
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; CHECK: liveins: $r2d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY [[COPY]]
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; CHECK-NEXT: [[VGBM:%[0-9]+]]:vr128bit = VGBM 0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64bit = COPY [[VGBM]].subreg_h64
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; CHECK-NEXT: $r0d = COPY [[COPY2]]
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; CHECK-NEXT: Return implicit $r0d
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%0:gr64bit = COPY $r2d
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%1:addr64bit = COPY %0
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%2:vr128bit = VGBM 0
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%3:gr64bit = COPY %2.subreg_h64
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$r0d = COPY %3
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Return implicit $r0d
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...

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