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[AArch64] add tests for funnel+or == 0; NFC
These are copied from x86 ( 1074bdf ) to provide more coverage for a potential generic combine.
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‎llvm/test/CodeGen/AArch64/setcc-fsh.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-- -o - %s | FileCheck %s
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declare i32 @llvm.fshl.i32(i32, i32, i32)
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declare i16 @llvm.fshr.i16(i16, i16, i16)
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declare i64 @llvm.fshr.i64(i64, i64, i64)
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declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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define i1 @fshl_or_eq_0(i32 %x, i32 %y) {
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; CHECK-LABEL: fshl_or_eq_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ror w8, w0, #27
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; CHECK-NEXT: orr w8, w8, w1, lsl #5
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%or = or i32 %x, %y
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%f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 5)
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%r = icmp eq i32 %f, 0
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ret i1 %r
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}
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define i1 @fshl_or_commute_eq_0(i32 %x, i32 %y) {
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; CHECK-LABEL: fshl_or_commute_eq_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ror w8, w0, #27
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; CHECK-NEXT: orr w8, w8, w1, lsl #5
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%or = or i32 %y, %x
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%f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 5)
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%r = icmp eq i32 %f, 0
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ret i1 %r
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}
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define <4 x i1> @fshl_or2_eq_0(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: fshl_or2_eq_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr v1.16b, v0.16b, v1.16b
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; CHECK-NEXT: shl v0.4s, v0.4s, #25
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; CHECK-NEXT: ushr v1.4s, v1.4s, #7
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; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%or = or <4 x i32> %x, %y
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %or, <4 x i32> <i32 25, i32 25, i32 25, i32 25>)
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%r = icmp eq <4 x i32> %f, zeroinitializer
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ret <4 x i1> %r
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}
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define <4 x i1> @fshl_or2_commute_eq_0(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: fshl_or2_commute_eq_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr v1.16b, v1.16b, v0.16b
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; CHECK-NEXT: shl v0.4s, v0.4s, #25
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; CHECK-NEXT: ushr v1.4s, v1.4s, #7
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; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%or = or <4 x i32> %y, %x
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %or, <4 x i32> <i32 25, i32 25, i32 25, i32 25>)
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%r = icmp eq <4 x i32> %f, zeroinitializer
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ret <4 x i1> %r
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}
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define i1 @fshr_or_eq_0(i16 %x, i16 %y) {
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; CHECK-LABEL: fshr_or_eq_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #16
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; CHECK-NEXT: orr w9, w0, w1
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; CHECK-NEXT: extr w8, w9, w8, #24
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; CHECK-NEXT: tst w8, #0xffff
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%or = or i16 %x, %y
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%f = call i16 @llvm.fshr.i16(i16 %or, i16 %x, i16 8)
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%r = icmp eq i16 %f, 0
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ret i1 %r
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}
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define i1 @fshr_or_commute_eq_0(i16 %x, i16 %y) {
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; CHECK-LABEL: fshr_or_commute_eq_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #16
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; CHECK-NEXT: orr w9, w1, w0
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; CHECK-NEXT: extr w8, w9, w8, #24
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; CHECK-NEXT: tst w8, #0xffff
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%or = or i16 %y, %x
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%f = call i16 @llvm.fshr.i16(i16 %or, i16 %x, i16 8)
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%r = icmp eq i16 %f, 0
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ret i1 %r
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}
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define i1 @fshr_or2_eq_0(i64 %x, i64 %y) {
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; CHECK-LABEL: fshr_or2_eq_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ror x8, x0, #3
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; CHECK-NEXT: orr x8, x8, x1, lsr #3
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; CHECK-NEXT: cmp x8, #0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%or = or i64 %x, %y
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%f = call i64 @llvm.fshr.i64(i64 %x, i64 %or, i64 3)
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%r = icmp eq i64 %f, 0
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ret i1 %r
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}
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define i1 @fshl_or_ne_0(i32 %x, i32 %y) {
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; CHECK-LABEL: fshl_or_ne_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ror w8, w0, #25
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; CHECK-NEXT: orr w8, w8, w1, lsl #7
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%or = or i32 %x, %y
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%f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 7)
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%r = icmp ne i32 %f, 0
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ret i1 %r
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}
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define i1 @fshl_or_commute_ne_0(i32 %x, i32 %y) {
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; CHECK-LABEL: fshl_or_commute_ne_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ror w8, w0, #25
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; CHECK-NEXT: orr w8, w8, w1, lsl #7
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%or = or i32 %y, %x
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%f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 7)
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%r = icmp ne i32 %f, 0
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ret i1 %r
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}
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define <4 x i1> @fshl_or2_ne_0(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: fshl_or2_ne_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr v1.16b, v0.16b, v1.16b
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; CHECK-NEXT: shl v0.4s, v0.4s, #5
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; CHECK-NEXT: ushr v1.4s, v1.4s, #27
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; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: cmtst v0.4s, v0.4s, v0.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%or = or <4 x i32> %x, %y
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %or, <4 x i32> <i32 5, i32 5, i32 5, i32 5>)
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%r = icmp ne <4 x i32> %f, zeroinitializer
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ret <4 x i1> %r
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}
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define <4 x i1> @fshl_or2_commute_ne_0(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: fshl_or2_commute_ne_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr v1.16b, v1.16b, v0.16b
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; CHECK-NEXT: shl v0.4s, v0.4s, #5
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; CHECK-NEXT: ushr v1.4s, v1.4s, #27
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; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: cmtst v0.4s, v0.4s, v0.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%or = or <4 x i32> %y, %x
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %or, <4 x i32> <i32 5, i32 5, i32 5, i32 5>)
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%r = icmp ne <4 x i32> %f, zeroinitializer
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ret <4 x i1> %r
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}
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define i1 @fshr_or_ne_0(i64 %x, i64 %y) {
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; CHECK-LABEL: fshr_or_ne_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w8, w0, w1
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; CHECK-NEXT: extr x8, x8, x0, #1
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; CHECK-NEXT: cmp x8, #0
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%or = or i64 %x, %y
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%f = call i64 @llvm.fshr.i64(i64 %or, i64 %x, i64 1)
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%r = icmp ne i64 %f, 0
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ret i1 %r
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}
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define i1 @fshr_or_commute_ne_0(i64 %x, i64 %y) {
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; CHECK-LABEL: fshr_or_commute_ne_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w8, w1, w0
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; CHECK-NEXT: extr x8, x8, x0, #1
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; CHECK-NEXT: cmp x8, #0
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%or = or i64 %y, %x
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%f = call i64 @llvm.fshr.i64(i64 %or, i64 %x, i64 1)
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%r = icmp ne i64 %f, 0
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ret i1 %r
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}
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define i1 @fshr_or2_ne_0(i16 %x, i16 %y) {
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; CHECK-LABEL: fshr_or2_ne_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w8, w0, w1
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; CHECK-NEXT: lsl w8, w8, #16
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; CHECK-NEXT: extr w8, w0, w8, #18
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; CHECK-NEXT: tst w8, #0xffff
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%or = or i16 %x, %y
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%f = call i16 @llvm.fshr.i16(i16 %x, i16 %or, i16 2)
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%r = icmp ne i16 %f, 0
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ret i1 %r
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}
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define i1 @fshr_or2_commute_ne_0(i16 %x, i16 %y) {
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; CHECK-LABEL: fshr_or2_commute_ne_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w8, w1, w0
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; CHECK-NEXT: lsl w8, w8, #16
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; CHECK-NEXT: extr w8, w0, w8, #18
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; CHECK-NEXT: tst w8, #0xffff
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%or = or i16 %y, %x
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%f = call i16 @llvm.fshr.i16(i16 %x, i16 %or, i16 2)
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%r = icmp ne i16 %f, 0
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ret i1 %r
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}
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define i1 @fshl_xor_eq_0(i32 %x, i32 %y) {
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; CHECK-LABEL: fshl_xor_eq_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: eor w8, w0, w1
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; CHECK-NEXT: extr w8, w8, w0, #30
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%or = xor i32 %x, %y
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%f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 2)
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%r = icmp eq i32 %f, 0
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ret i1 %r
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}
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define i1 @fshl_or_sgt_0(i32 %x, i32 %y) {
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; CHECK-LABEL: fshl_or_sgt_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ror w8, w0, #30
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; CHECK-NEXT: orr w8, w8, w1, lsl #2
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: cset w0, gt
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; CHECK-NEXT: ret
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%or = or i32 %x, %y
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%f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 2)
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%r = icmp sgt i32 %f, 0
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ret i1 %r
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}
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define i1 @fshl_or_ne_2(i32 %x, i32 %y) {
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; CHECK-LABEL: fshl_or_ne_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ror w8, w0, #30
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; CHECK-NEXT: orr w8, w8, w1, lsl #2
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; CHECK-NEXT: cmp w8, #2
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%or = or i32 %x, %y
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%f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 2)
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%r = icmp ne i32 %f, 2
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ret i1 %r
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}

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