@@ -199,8 +199,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
199
199
ParseStatus parseInsnDirectiveOpcode (OperandVector &Operands);
200
200
ParseStatus parseInsnCDirectiveOpcode (OperandVector &Operands);
201
201
ParseStatus parseGPRAsFPR (OperandVector &Operands);
202
- template <bool IsRV64Inst>
203
- ParseStatus parseGPRPair (OperandVector &Operands);
202
+ template <bool IsRV64Inst> ParseStatus parseGPRPair (OperandVector &Operands);
204
203
ParseStatus parseGPRPair (OperandVector &Operands, bool IsRV64Inst);
205
204
ParseStatus parseFRMArg (OperandVector &Operands);
206
205
ParseStatus parseFenceArg (OperandVector &Operands);
@@ -471,7 +470,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
471
470
472
471
bool isGPRPair () const {
473
472
return Kind == KindTy::Register &&
474
- RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains (Reg.RegNum );
473
+ RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains (
474
+ Reg.RegNum );
475
475
}
476
476
477
477
static bool evaluateConstantImm (const MCExpr *Expr, int64_t &Imm,
@@ -2269,8 +2269,9 @@ ParseStatus RISCVAsmParser::parseGPRPair(OperandVector &Operands,
2269
2269
getLexer ().Lex ();
2270
2270
2271
2271
const MCRegisterInfo *RI = getContext ().getRegisterInfo ();
2272
- unsigned Pair = RI->getMatchingSuperReg (RegNo, RISCV::sub_gpr_even,
2273
- &RISCVMCRegisterClasses[RISCV::GPRPairRegClassID]);
2272
+ unsigned Pair = RI->getMatchingSuperReg (
2273
+ RegNo, RISCV::sub_gpr_even,
2274
+ &RISCVMCRegisterClasses[RISCV::GPRPairRegClassID]);
2274
2275
Operands.push_back (RISCVOperand::createReg (Pair, S, E));
2275
2276
return ParseStatus::Success;
2276
2277
}
0 commit comments