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[RISCV] Pre-commit tests for D132614. NFC
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‎llvm/test/CodeGen/RISCV/setcc-logic.ll

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@@ -118,3 +118,195 @@ define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind {
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%r = and i1 %a, %b
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ret i1 %r
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}
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define i1 @and_icmp_sge(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
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; RV32I-LABEL: and_icmp_sge:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slt a0, a0, a1
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; RV32I-NEXT: not a0, a0
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; RV32I-NEXT: slt a1, a2, a3
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; RV32I-NEXT: xori a1, a1, 1
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_icmp_sge:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slt a0, a0, a1
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; RV64I-NEXT: not a0, a0
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; RV64I-NEXT: slt a1, a2, a3
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; RV64I-NEXT: xori a1, a1, 1
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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%cmp1 = icmp sge i32 %a, %b
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%cmp2 = icmp sge i32 %c, %d
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%and = and i1 %cmp1, %cmp2
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ret i1 %and
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}
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define i1 @and_icmp_sle(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
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; RV32I-LABEL: and_icmp_sle:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slt a0, a1, a0
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; RV32I-NEXT: not a0, a0
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; RV32I-NEXT: slt a1, a3, a2
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; RV32I-NEXT: xori a1, a1, 1
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_icmp_sle:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slt a0, a1, a0
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; RV64I-NEXT: not a0, a0
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; RV64I-NEXT: slt a1, a3, a2
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; RV64I-NEXT: xori a1, a1, 1
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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%cmp1 = icmp sle i32 %a, %b
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%cmp2 = icmp sle i32 %c, %d
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%and = and i1 %cmp1, %cmp2
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ret i1 %and
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}
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define i1 @and_icmp_uge(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
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; RV32I-LABEL: and_icmp_uge:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: not a0, a0
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; RV32I-NEXT: sltu a1, a2, a3
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; RV32I-NEXT: xori a1, a1, 1
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_icmp_uge:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: not a0, a0
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; RV64I-NEXT: sltu a1, a2, a3
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; RV64I-NEXT: xori a1, a1, 1
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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%cmp1 = icmp uge i32 %a, %b
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%cmp2 = icmp uge i32 %c, %d
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%and = and i1 %cmp1, %cmp2
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ret i1 %and
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}
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define i1 @and_icmp_ule(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
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; RV32I-LABEL: and_icmp_ule:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a0, a1, a0
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; RV32I-NEXT: not a0, a0
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; RV32I-NEXT: sltu a1, a3, a2
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; RV32I-NEXT: xori a1, a1, 1
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_icmp_ule:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a0, a1, a0
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; RV64I-NEXT: not a0, a0
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; RV64I-NEXT: sltu a1, a3, a2
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; RV64I-NEXT: xori a1, a1, 1
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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%cmp1 = icmp ule i32 %a, %b
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%cmp2 = icmp ule i32 %c, %d
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%and = and i1 %cmp1, %cmp2
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ret i1 %and
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}
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define i1 @or_icmp_sge(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
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; RV32I-LABEL: or_icmp_sge:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slt a0, a0, a1
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; RV32I-NEXT: xori a0, a0, 1
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; RV32I-NEXT: slt a1, a2, a3
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; RV32I-NEXT: xori a1, a1, 1
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: or_icmp_sge:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slt a0, a0, a1
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; RV64I-NEXT: xori a0, a0, 1
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; RV64I-NEXT: slt a1, a2, a3
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; RV64I-NEXT: xori a1, a1, 1
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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%cmp1 = icmp sge i32 %a, %b
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%cmp2 = icmp sge i32 %c, %d
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%and = or i1 %cmp1, %cmp2
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ret i1 %and
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}
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define i1 @or_icmp_sle(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
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; RV32I-LABEL: or_icmp_sle:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slt a0, a1, a0
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; RV32I-NEXT: xori a0, a0, 1
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; RV32I-NEXT: slt a1, a3, a2
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; RV32I-NEXT: xori a1, a1, 1
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: or_icmp_sle:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slt a0, a1, a0
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; RV64I-NEXT: xori a0, a0, 1
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; RV64I-NEXT: slt a1, a3, a2
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; RV64I-NEXT: xori a1, a1, 1
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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%cmp1 = icmp sle i32 %a, %b
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%cmp2 = icmp sle i32 %c, %d
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%and = or i1 %cmp1, %cmp2
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ret i1 %and
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}
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define i1 @or_icmp_uge(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
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; RV32I-LABEL: or_icmp_uge:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: xori a0, a0, 1
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; RV32I-NEXT: sltu a1, a2, a3
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; RV32I-NEXT: xori a1, a1, 1
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: or_icmp_uge:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: xori a0, a0, 1
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; RV64I-NEXT: sltu a1, a2, a3
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; RV64I-NEXT: xori a1, a1, 1
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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%cmp1 = icmp uge i32 %a, %b
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%cmp2 = icmp uge i32 %c, %d
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%and = or i1 %cmp1, %cmp2
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ret i1 %and
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}
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define i1 @or_icmp_ule(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
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; RV32I-LABEL: or_icmp_ule:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a0, a1, a0
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; RV32I-NEXT: xori a0, a0, 1
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; RV32I-NEXT: sltu a1, a3, a2
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; RV32I-NEXT: xori a1, a1, 1
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: or_icmp_ule:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sltu a0, a1, a0
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; RV64I-NEXT: xori a0, a0, 1
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; RV64I-NEXT: sltu a1, a3, a2
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; RV64I-NEXT: xori a1, a1, 1
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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%cmp1 = icmp ule i32 %a, %b
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%cmp2 = icmp ule i32 %c, %d
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%and = or i1 %cmp1, %cmp2
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ret i1 %and
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}

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