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[RISCV] Merge bf16 tests into respective tests. NFC
I added these in #108245, but given the sheer number of tests that will need to be added to cover bf16 promotion to f32 it seems better to keep them in one place to avoid an explosion of files.
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‎llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode-bf16.ll

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This file was deleted.

‎llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll

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Original file line numberDiff line numberDiff line change
@@ -1,12 +1,88 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
8-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \
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; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFH
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \
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; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFH
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \
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; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFHMIN
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \
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; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFHMIN
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define <vscale x 1 x bfloat> @nxv1bf16(<vscale x 1 x bfloat> %v) {
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; CHECK-LABEL: nxv1bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: ret
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%r = call <vscale x 1 x bfloat> @llvm.fabs.nxv1bf16(<vscale x 1 x bfloat> %v)
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ret <vscale x 1 x bfloat> %r
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}
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define <vscale x 2 x bfloat> @nxv2bf16(<vscale x 2 x bfloat> %v) {
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; CHECK-LABEL: nxv2bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: ret
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%r = call <vscale x 2 x bfloat> @llvm.fabs.nxv2bf16(<vscale x 2 x bfloat> %v)
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ret <vscale x 2 x bfloat> %r
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}
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define <vscale x 4 x bfloat> @nxv4bf16(<vscale x 4 x bfloat> %v) {
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; CHECK-LABEL: nxv4bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: ret
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%r = call <vscale x 4 x bfloat> @llvm.fabs.nxv4bf16(<vscale x 4 x bfloat> %v)
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ret <vscale x 4 x bfloat> %r
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}
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define <vscale x 8 x bfloat> @nxv8bf16(<vscale x 8 x bfloat> %v) {
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; CHECK-LABEL: nxv8bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: ret
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%r = call <vscale x 8 x bfloat> @llvm.fabs.nxv8bf16(<vscale x 8 x bfloat> %v)
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ret <vscale x 8 x bfloat> %r
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}
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define <vscale x 16 x bfloat> @nxv16bf16(<vscale x 16 x bfloat> %v) {
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; CHECK-LABEL: nxv16bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: ret
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%r = call <vscale x 16 x bfloat> @llvm.fabs.nxv16bf16(<vscale x 16 x bfloat> %v)
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ret <vscale x 16 x bfloat> %r
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}
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define <vscale x 32 x bfloat> @nxv32bf16(<vscale x 32 x bfloat> %v) {
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; CHECK-LABEL: nxv32bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: ret
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%r = call <vscale x 32 x bfloat> @llvm.fabs.nxv32bf16(<vscale x 32 x bfloat> %v)
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ret <vscale x 32 x bfloat> %r
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}
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declare <vscale x 1 x half> @llvm.fabs.nxv1f16(<vscale x 1 x half>)
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‎llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode-bf16.ll

Lines changed: 0 additions & 87 deletions
This file was deleted.

‎llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll

Lines changed: 96 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,100 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
3-
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
4-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
5-
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
6-
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=ilp32d \
7-
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
8-
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
2+
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \
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; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFH
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \
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; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFH
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \
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; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFHMIN
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \
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; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFHMIN
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define <vscale x 1 x bfloat> @nxv1bf16(<vscale x 1 x bfloat> %vm, <vscale x 1 x bfloat> %vs) {
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; CHECK-LABEL: nxv1bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vor.vv v8, v8, v9
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; CHECK-NEXT: ret
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%r = call <vscale x 1 x bfloat> @llvm.copysign.nxv1bf16(<vscale x 1 x bfloat> %vm, <vscale x 1 x bfloat> %vs)
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ret <vscale x 1 x bfloat> %r
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}
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define <vscale x 2 x bfloat> @nxv2bf16(<vscale x 2 x bfloat> %vm, <vscale x 2 x bfloat> %vs) {
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; CHECK-LABEL: nxv2bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vor.vv v8, v8, v9
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; CHECK-NEXT: ret
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%r = call <vscale x 2 x bfloat> @llvm.copysign.nxv2bf16(<vscale x 2 x bfloat> %vm, <vscale x 2 x bfloat> %vs)
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ret <vscale x 2 x bfloat> %r
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}
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define <vscale x 4 x bfloat> @nxv4bf16(<vscale x 4 x bfloat> %vm, <vscale x 4 x bfloat> %vs) {
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; CHECK-LABEL: nxv4bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
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; CHECK-NEXT: vand.vx v9, v9, a0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vor.vv v8, v8, v9
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; CHECK-NEXT: ret
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%r = call <vscale x 4 x bfloat> @llvm.copysign.nxv4bf16(<vscale x 4 x bfloat> %vm, <vscale x 4 x bfloat> %vs)
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ret <vscale x 4 x bfloat> %r
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}
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define <vscale x 8 x bfloat> @nxv8bf16(<vscale x 8 x bfloat> %vm, <vscale x 8 x bfloat> %vs) {
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; CHECK-LABEL: nxv8bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
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; CHECK-NEXT: vand.vx v10, v10, a0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vor.vv v8, v8, v10
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; CHECK-NEXT: ret
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%r = call <vscale x 8 x bfloat> @llvm.copysign.nxv8bf16(<vscale x 8 x bfloat> %vm, <vscale x 8 x bfloat> %vs)
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ret <vscale x 8 x bfloat> %r
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}
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define <vscale x 16 x bfloat> @nxv16bf16(<vscale x 16 x bfloat> %vm, <vscale x 16 x bfloat> %vs) {
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; CHECK-LABEL: nxv16bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
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; CHECK-NEXT: vand.vx v12, v12, a0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vor.vv v8, v8, v12
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; CHECK-NEXT: ret
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%r = call <vscale x 16 x bfloat> @llvm.copysign.nxv16bf16(<vscale x 16 x bfloat> %vm, <vscale x 16 x bfloat> %vs)
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ret <vscale x 16 x bfloat> %r
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}
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define <vscale x 32 x bfloat> @nxv32bf32(<vscale x 32 x bfloat> %vm, <vscale x 32 x bfloat> %vs) {
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; CHECK-LABEL: nxv32bf32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
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; CHECK-NEXT: vand.vx v16, v16, a0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vor.vv v8, v8, v16
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; CHECK-NEXT: ret
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%r = call <vscale x 32 x bfloat> @llvm.copysign.nxv32bf32(<vscale x 32 x bfloat> %vm, <vscale x 32 x bfloat> %vs)
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ret <vscale x 32 x bfloat> %r
97+
}
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declare <vscale x 1 x half> @llvm.copysign.nxv1f16(<vscale x 1 x half>, <vscale x 1 x half>)
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