Add tuning feature for p470 and p670

Author: lukel97

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -1357,6 +1357,11 @@ def TuneOptimizedZeroStrideLoad
                       "true", "Optimized (perform fewer memory operations)"
                       "zero-stride vector load">;
 
+def TuneOptimizedVectorGather
+   : SubtargetFeature<"optimized-vector-gather", "HasOptimizedVectorGather",
+                      "true", "At LMUL > 1 vrgather.vv doesn't read from"
+                      "registers that have no indices">;
+
 def Experimental
    : SubtargetFeature<"experimental", "HasExperimental",
                       "true", "Experimental intrinsics">;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -10331,10 +10331,11 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
   MVT XLenVT = Subtarget.getXLenVT();
   auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
 
-  // On most uarchs vrgather.vv is quadratic in LMUL because each output
-  // register may read from LMUL registers. However to reverse a vector each
-  // output register only needs to read from one register. So decompose it into
-  // LMUL * M1 vrgather.vvs, so we get O(LMUL) performance instead of O(LMUL^2).
+  // On some uarchs vrgather.vv will read from every input register for each
+  // output register, regardless of the indices. However to reverse a vector
+  // each output register only needs to read from one register. So decompose it
+  // into LMUL * M1 vrgather.vvs, so we get O(LMUL) performance instead of
+  // O(LMUL^2).
   //
   // vsetvli a1, zero, e64, m4, ta, ma
   // vrgatherei16.vv v12, v8, v16
@@ -10344,7 +10345,8 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
   // vrgather.vv v14, v9, v16
   // vrgather.vv v13, v10, v16
   // vrgather.vv v12, v11, v16
-  if (ContainerVT.bitsGT(getLMUL1VT(ContainerVT)) &&
+  if (!Subtarget.hasOptimizedVectorGather() &&
+      ContainerVT.bitsGT(getLMUL1VT(ContainerVT)) &&
       ContainerVT.getVectorElementCount().isKnownMultipleOf(2)) {
     auto [Lo, Hi] = DAG.SplitVector(Vec, DL);
     Lo = DAG.getNode(ISD::VECTOR_REVERSE, DL, Lo.getSimpleValueType(), Lo);

llvm/lib/Target/RISCV/RISCVProcessors.td

@@ -269,7 +269,8 @@ def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,
                                        FeatureUnalignedScalarMem,
                                        FeatureUnalignedVectorMem]),
                                       !listconcat(SiFiveP400TuneFeatures,
-                                                  [TuneNoSinkSplatOperands])>;
+                                                  [TuneNoSinkSplatOperands,
+                                                   TuneOptimizedVectorGather])>;
 
 
 def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
@@ -290,6 +291,7 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
                                        TuneLUIADDIFusion,
                                        TuneAUIPCADDIFusion,
                                        TuneNoSinkSplatOperands,
+                                       TuneOptimizedVectorGather,
                                        FeaturePostRAScheduler]>;
 
 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",

llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll

@@ -2014,3 +2014,19 @@ declare <vscale x 8 x double> @llvm.vector.reverse.nxv8f64(<vscale x 8 x double>
 declare <vscale x 3 x i64> @llvm.vector.reverse.nxv3i64(<vscale x 3 x i64>)
 declare <vscale x 6 x i64> @llvm.vector.reverse.nxv6i64(<vscale x 6 x i64>)
 declare <vscale x 12 x i64> @llvm.vector.reverse.nxv12i64(<vscale x 12 x i64>)
+
+define <vscale x 8 x i64> @reverse_nxv8i64_optimized_vector_gather(<vscale x 8 x i64> %a) "target-features"="+optimized-vector-gather" {
+; CHECK-LABEL: reverse_nxv8i64_optimized_vector_gather:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    csrr a0, vlenb
+; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vid.v v16
+; CHECK-NEXT:    vrsub.vx v24, v16, a0
+; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
+; CHECK-NEXT:    vrgatherei16.vv v16, v8, v24
+; CHECK-NEXT:    vmv.v.v v8, v16
+; CHECK-NEXT:    ret
+  %res = call <vscale x 8 x i64> @llvm.vector.reverse.nxv8i64(<vscale x 8 x i64> %a)
+  ret <vscale x 8 x i64> %res
+}