[Target][RISCV] Update SubtargetFeature definition for RV32/RV64 (NFCI).

This is done for consistency with other Predicate/Subtargetfeature
pairs, where the second parameter of the SubtargetFeature correspond
to the NAME of the def of the Predicate associated to the
SubtargetFeature.

Differential Revision: https://reviews.llvm.org/D146129

Author: fpetrogalli

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -576,9 +576,9 @@ def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
 // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
 // tuning CPU names.
 def Feature32Bit
-    : SubtargetFeature<"32bit", "HasRV32", "true", "Implements RV32">;
+    : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
 def Feature64Bit
-    : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
+    : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">;
 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of Feature64Bit),
                                          "RV64I Base Instruction Set">;

llvm/lib/Target/RISCV/RISCVSubtarget.h

@@ -114,7 +114,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool hasStdExtCOrZca() const { return HasStdExtC || HasStdExtZca; }
   bool hasStdExtZvl() const { return ZvlLen != 0; }
   bool hasStdExtZfhOrZfhmin() const { return HasStdExtZfh || HasStdExtZfhmin; }
-  bool is64Bit() const { return HasRV64; }
+  bool is64Bit() const { return IsRV64; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
   unsigned getFLen() const {