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fix irreflexible iterator assert
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4 files changed

+169
-161
lines changed

4 files changed

+169
-161
lines changed

‎llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp

Lines changed: 15 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -125,22 +125,21 @@ class PartialOrderingVisitor {
125125
Visited.insert(BB);
126126

127127
SmallVector<BasicBlock *, 2> OtherSuccessors;
128-
BasicBlock *LoopSuccessor = nullptr;
128+
SmallVector<BasicBlock *, 2> LoopSuccessors;
129129

130130
for (BasicBlock *Successor : successors(BB)) {
131131
// Ignoring back-edges.
132132
if (DT.dominates(Successor, BB))
133133
continue;
134134

135135
if (isLoopHeader && L->contains(Successor)) {
136-
assert(LoopSuccessor == nullptr);
137-
LoopSuccessor = Successor;
136+
LoopSuccessors.push_back(Successor);
138137
} else
139138
OtherSuccessors.push_back(Successor);
140139
}
141140

142-
if (LoopSuccessor)
143-
Rank = visit(LoopSuccessor, Rank + 1);
141+
for (BasicBlock *BB : LoopSuccessors)
142+
Rank = std::max(Rank, visit(BB, Rank + 1));
144143

145144
size_t OutputRank = Rank;
146145
for (BasicBlock *Item : OtherSuccessors)
@@ -167,6 +166,10 @@ class PartialOrderingVisitor {
167166
B2R[Order[i].first] = i;
168167
}
169168

169+
size_t getRank(BasicBlock *BB) {
170+
return B2R[BB];
171+
}
172+
170173
// Visit the function starting from the basic block |Start|, and calling |Op|
171174
// on each visited BB. This traversal ignores back-edges, meaning this won't
172175
// visit a node to which |Start| is not an ancestor.
@@ -839,12 +842,14 @@ class SPIRVStructurizer : public FunctionPass {
839842

840843
Instruction *InsertionPoint = *MergeInstructions.begin();
841844

842-
DomTreeBuilder::BBPostDomTree PDT;
843-
PDT.recalculate(F);
845+
PartialOrderingVisitor Visitor(F);
844846
std::sort(MergeInstructions.begin(), MergeInstructions.end(),
845-
[&PDT](Instruction *Left, Instruction *Right) {
846-
return PDT.dominates(getDesignatedMergeBlock(Right),
847-
getDesignatedMergeBlock(Left));
847+
[&Visitor](Instruction *Left, Instruction *Right) {
848+
if (Left == Right)
849+
return true;
850+
BasicBlock *RightMerge = getDesignatedMergeBlock(Right);
851+
BasicBlock *LeftMerge = getDesignatedMergeBlock(Left);
852+
return Visitor.getRank(RightMerge) >= Visitor.getRank(LeftMerge);
848853
});
849854

850855
for (Instruction *I : MergeInstructions) {

‎llvm/test/CodeGen/SPIRV/structurizer/cf.do.continue.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
; RUN: %if spirv-tools %{ llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-as --preserve-numeric-ids - -o - | spirv-val %}
21
; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=10
2+
; RUN: %if spirv-tools %{ llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-as --preserve-numeric-ids - -o - | spirv-val %}
33
;
44
; Source HLSL:
55
;

‎llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.ll

Lines changed: 102 additions & 101 deletions
Original file line numberDiff line numberDiff line change
@@ -123,143 +123,144 @@
123123
; process();
124124
; }
125125

126+
126127
; CHECK: %[[#func_22:]] = OpFunction %[[#uint:]] DontInline %[[#]]
127-
; CHECK: %[[#bb94:]] = OpLabel
128+
; CHECK: %[[#bb96:]] = OpLabel
128129
; CHECK: OpReturnValue %[[#]]
129130
; CHECK: OpFunctionEnd
130131
; CHECK: %[[#func_23:]] = OpFunction %[[#uint:]] DontInline %[[#]]
131-
; CHECK: %[[#bb95:]] = OpLabel
132-
; CHECK: OpSelectionMerge %[[#bb96:]] None
133-
; CHECK: OpBranchConditional %[[#]] %[[#bb97:]] %[[#bb98:]]
134-
; CHECK: %[[#bb98:]] = OpLabel
135132
; CHECK: %[[#bb97:]] = OpLabel
136-
; CHECK: OpSelectionMerge %[[#bb99:]] None
137-
; CHECK: OpSwitch %[[#]] %[[#bb100:]] 1 %[[#bb99:]] 2 %[[#bb101:]]
138-
; CHECK: %[[#bb101:]] = OpLabel
139-
; CHECK: OpBranch %[[#bb99:]]
133+
; CHECK: OpSelectionMerge %[[#bb98:]] None
134+
; CHECK: OpBranchConditional %[[#]] %[[#bb99:]] %[[#bb100:]]
135+
; CHECK: %[[#bb100:]] = OpLabel
140136
; CHECK: %[[#bb99:]] = OpLabel
141-
; CHECK: OpBranchConditional %[[#]] %[[#bb102:]] %[[#bb96:]]
142-
; CHECK: %[[#bb96:]] = OpLabel
143-
; CHECK: OpSelectionMerge %[[#bb103:]] None
144-
; CHECK: OpBranchConditional %[[#]] %[[#bb104:]] %[[#bb105:]]
145-
; CHECK: %[[#bb105:]] = OpLabel
146-
; CHECK: %[[#bb104:]] = OpLabel
147-
; CHECK: OpSelectionMerge %[[#bb106:]] None
148-
; CHECK: OpSwitch %[[#]] %[[#bb106:]] 10 %[[#bb107:]] 20 %[[#bb108:]]
149-
; CHECK: %[[#bb108:]] = OpLabel
150-
; CHECK: OpBranch %[[#bb106:]]
137+
; CHECK: OpSelectionMerge %[[#bb101:]] None
138+
; CHECK: OpSwitch %[[#]] %[[#bb102:]] 1 %[[#bb101:]] 2 %[[#bb103:]]
139+
; CHECK: %[[#bb103:]] = OpLabel
140+
; CHECK: OpBranch %[[#bb101:]]
141+
; CHECK: %[[#bb101:]] = OpLabel
142+
; CHECK: OpBranchConditional %[[#]] %[[#bb104:]] %[[#bb98:]]
143+
; CHECK: %[[#bb98:]] = OpLabel
144+
; CHECK: OpSelectionMerge %[[#bb105:]] None
145+
; CHECK: OpBranchConditional %[[#]] %[[#bb106:]] %[[#bb107:]]
151146
; CHECK: %[[#bb107:]] = OpLabel
152-
; CHECK: OpBranch %[[#bb106:]]
153147
; CHECK: %[[#bb106:]] = OpLabel
154-
; CHECK: OpBranchConditional %[[#]] %[[#bb109:]] %[[#bb103:]]
155-
; CHECK: %[[#bb103:]] = OpLabel
156-
; CHECK: OpBranch %[[#bb110:]]
148+
; CHECK: OpSelectionMerge %[[#bb108:]] None
149+
; CHECK: OpSwitch %[[#]] %[[#bb108:]] 10 %[[#bb109:]] 20 %[[#bb110:]]
157150
; CHECK: %[[#bb110:]] = OpLabel
158-
; CHECK: OpSelectionMerge %[[#bb111:]] None
159-
; CHECK: OpBranchConditional %[[#]] %[[#bb112:]] %[[#bb113:]]
160-
; CHECK: %[[#bb113:]] = OpLabel
151+
; CHECK: OpBranch %[[#bb108:]]
152+
; CHECK: %[[#bb109:]] = OpLabel
153+
; CHECK: OpBranch %[[#bb108:]]
154+
; CHECK: %[[#bb108:]] = OpLabel
155+
; CHECK: OpBranchConditional %[[#]] %[[#bb111:]] %[[#bb105:]]
156+
; CHECK: %[[#bb105:]] = OpLabel
157+
; CHECK: OpBranch %[[#bb112:]]
161158
; CHECK: %[[#bb112:]] = OpLabel
162-
; CHECK: OpSelectionMerge %[[#bb114:]] None
163-
; CHECK: OpBranchConditional %[[#]] %[[#bb115:]] %[[#bb116:]]
164-
; CHECK: %[[#bb116:]] = OpLabel
159+
; CHECK: OpSelectionMerge %[[#bb113:]] None
160+
; CHECK: OpBranchConditional %[[#]] %[[#bb114:]] %[[#bb115:]]
165161
; CHECK: %[[#bb115:]] = OpLabel
166-
; CHECK: OpSelectionMerge %[[#bb117:]] None
167-
; CHECK: OpBranchConditional %[[#]] %[[#bb118:]] %[[#bb119:]]
168-
; CHECK: %[[#bb119:]] = OpLabel
162+
; CHECK: %[[#bb114:]] = OpLabel
163+
; CHECK: OpSelectionMerge %[[#bb116:]] None
164+
; CHECK: OpBranchConditional %[[#]] %[[#bb117:]] %[[#bb118:]]
169165
; CHECK: %[[#bb118:]] = OpLabel
170-
; CHECK: OpSelectionMerge %[[#bb120:]] None
171-
; CHECK: OpSwitch %[[#]] %[[#bb121:]] 1 %[[#bb122:]] 2 %[[#bb120:]] 3 %[[#bb123:]] 140 %[[#bb124:]] 4 %[[#bb125:]] 5 %[[#bb126:]] 6 %[[#bb127:]] 7 %[[#bb128:]]
166+
; CHECK: %[[#bb117:]] = OpLabel
167+
; CHECK: OpSelectionMerge %[[#bb119:]] None
168+
; CHECK: OpBranchConditional %[[#]] %[[#bb120:]] %[[#bb121:]]
169+
; CHECK: %[[#bb121:]] = OpLabel
170+
; CHECK: %[[#bb120:]] = OpLabel
171+
; CHECK: OpSelectionMerge %[[#bb122:]] None
172+
; CHECK: OpSwitch %[[#]] %[[#bb123:]] 1 %[[#bb124:]] 2 %[[#bb122:]] 3 %[[#bb125:]] 140 %[[#bb126:]] 4 %[[#bb127:]] 5 %[[#bb128:]] 6 %[[#bb129:]] 7 %[[#bb130:]]
173+
; CHECK: %[[#bb130:]] = OpLabel
174+
; CHECK: OpBranch %[[#bb122:]]
175+
; CHECK: %[[#bb129:]] = OpLabel
176+
; CHECK: OpBranch %[[#bb122:]]
172177
; CHECK: %[[#bb128:]] = OpLabel
173-
; CHECK: OpBranch %[[#bb120:]]
178+
; CHECK: OpBranch %[[#bb122:]]
174179
; CHECK: %[[#bb127:]] = OpLabel
175-
; CHECK: OpBranch %[[#bb120:]]
180+
; CHECK: OpBranch %[[#bb122:]]
176181
; CHECK: %[[#bb126:]] = OpLabel
177-
; CHECK: OpBranch %[[#bb120:]]
182+
; CHECK: OpBranch %[[#bb122:]]
178183
; CHECK: %[[#bb125:]] = OpLabel
179-
; CHECK: OpBranch %[[#bb120:]]
180-
; CHECK: %[[#bb124:]] = OpLabel
181-
; CHECK: OpBranch %[[#bb120:]]
182-
; CHECK: %[[#bb123:]] = OpLabel
183-
; CHECK: OpBranch %[[#bb120:]]
184-
; CHECK: %[[#bb120:]] = OpLabel
185-
; CHECK: OpSelectionMerge %[[#bb129:]] None
186-
; CHECK: OpSwitch %[[#]] %[[#bb130:]] 1 %[[#bb129:]] 2 %[[#bb131:]] 3 %[[#bb132:]]
184+
; CHECK: OpBranch %[[#bb122:]]
185+
; CHECK: %[[#bb122:]] = OpLabel
186+
; CHECK: OpSelectionMerge %[[#bb131:]] None
187+
; CHECK: OpSwitch %[[#]] %[[#bb131:]] 1 %[[#bb132:]] 2 %[[#bb133:]] 3 %[[#bb134:]]
188+
; CHECK: %[[#bb134:]] = OpLabel
189+
; CHECK: OpBranch %[[#bb131:]]
190+
; CHECK: %[[#bb133:]] = OpLabel
191+
; CHECK: OpBranch %[[#bb131:]]
187192
; CHECK: %[[#bb132:]] = OpLabel
188-
; CHECK: OpBranch %[[#bb129:]]
193+
; CHECK: OpBranch %[[#bb131:]]
189194
; CHECK: %[[#bb131:]] = OpLabel
190-
; CHECK: OpBranch %[[#bb129:]]
191-
; CHECK: %[[#bb129:]] = OpLabel
192-
; CHECK: OpBranch %[[#bb117:]]
193-
; CHECK: %[[#bb117:]] = OpLabel
194-
; CHECK: OpSelectionMerge %[[#bb133:]] None
195-
; CHECK: OpSwitch %[[#]] %[[#bb134:]] 1 %[[#bb133:]] 2 %[[#bb135:]]
196-
; CHECK: %[[#bb135:]] = OpLabel
197-
; CHECK: OpBranch %[[#bb133:]]
198-
; CHECK: %[[#bb133:]] = OpLabel
199-
; CHECK: OpBranch %[[#bb114:]]
200-
; CHECK: %[[#bb114:]] = OpLabel
201-
; CHECK: OpBranch %[[#bb111:]]
202-
; CHECK: %[[#bb111:]] = OpLabel
203-
; CHECK: OpSelectionMerge %[[#bb136:]] None
204-
; CHECK: OpBranchConditional %[[#]] %[[#bb137:]] %[[#bb136:]]
195+
; CHECK: OpBranch %[[#bb119:]]
196+
; CHECK: %[[#bb119:]] = OpLabel
197+
; CHECK: OpSelectionMerge %[[#bb135:]] None
198+
; CHECK: OpSwitch %[[#]] %[[#bb135:]] 1 %[[#bb136:]] 2 %[[#bb137:]]
199+
; CHECK: %[[#bb137:]] = OpLabel
200+
; CHECK: OpBranch %[[#bb135:]]
205201
; CHECK: %[[#bb136:]] = OpLabel
206-
; CHECK: OpBranch %[[#bb138:]]
207-
; CHECK: %[[#bb138:]] = OpLabel
208-
; CHECK: OpBranch %[[#bb139:]]
202+
; CHECK: OpBranch %[[#bb135:]]
203+
; CHECK: %[[#bb135:]] = OpLabel
204+
; CHECK: OpBranch %[[#bb116:]]
205+
; CHECK: %[[#bb116:]] = OpLabel
206+
; CHECK: OpBranchConditional %[[#]] %[[#bb138:]] %[[#bb113:]]
207+
; CHECK: %[[#bb113:]] = OpLabel
208+
; CHECK: OpSelectionMerge %[[#bb139:]] None
209+
; CHECK: OpBranchConditional %[[#]] %[[#bb140:]] %[[#bb139:]]
209210
; CHECK: %[[#bb139:]] = OpLabel
210-
; CHECK: OpSelectionMerge %[[#bb140:]] None
211-
; CHECK: OpBranchConditional %[[#]] %[[#bb141:]] %[[#bb142:]]
212-
; CHECK: %[[#bb142:]] = OpLabel
211+
; CHECK: OpBranch %[[#bb141:]]
213212
; CHECK: %[[#bb141:]] = OpLabel
213+
; CHECK: OpBranch %[[#bb142:]]
214+
; CHECK: %[[#bb142:]] = OpLabel
214215
; CHECK: OpSelectionMerge %[[#bb143:]] None
215-
; CHECK: OpSwitch %[[#]] %[[#bb143:]] 300 %[[#bb144:]] 400 %[[#bb145:]]
216+
; CHECK: OpBranchConditional %[[#]] %[[#bb144:]] %[[#bb145:]]
216217
; CHECK: %[[#bb145:]] = OpLabel
217-
; CHECK: OpBranch %[[#bb143:]]
218218
; CHECK: %[[#bb144:]] = OpLabel
219-
; CHECK: OpBranch %[[#bb143:]]
220-
; CHECK: %[[#bb143:]] = OpLabel
221-
; CHECK: OpBranchConditional %[[#]] %[[#bb140:]] %[[#bb146:]]
219+
; CHECK: OpSelectionMerge %[[#bb146:]] None
220+
; CHECK: OpSwitch %[[#]] %[[#bb146:]] 300 %[[#bb147:]] 400 %[[#bb148:]]
221+
; CHECK: %[[#bb148:]] = OpLabel
222+
; CHECK: OpBranch %[[#bb146:]]
223+
; CHECK: %[[#bb147:]] = OpLabel
224+
; CHECK: OpBranch %[[#bb146:]]
222225
; CHECK: %[[#bb146:]] = OpLabel
223-
; CHECK: OpSelectionMerge %[[#bb147:]] None
224-
; CHECK: OpSwitch %[[#]] %[[#bb147:]] 500 %[[#bb148:]] 600 %[[#bb149:]]
226+
; CHECK: OpBranchConditional %[[#]] %[[#bb143:]] %[[#bb149:]]
225227
; CHECK: %[[#bb149:]] = OpLabel
228+
; CHECK: OpSelectionMerge %[[#bb150:]] None
229+
; CHECK: OpSwitch %[[#]] %[[#bb150:]] 500 %[[#bb151:]] 600 %[[#bb152:]]
230+
; CHECK: %[[#bb152:]] = OpLabel
231+
; CHECK: OpBranch %[[#bb153:]]
232+
; CHECK: %[[#bb153:]] = OpLabel
233+
; CHECK: OpBranch %[[#bb150:]]
234+
; CHECK: %[[#bb151:]] = OpLabel
226235
; CHECK: OpBranch %[[#bb150:]]
227236
; CHECK: %[[#bb150:]] = OpLabel
228-
; CHECK: OpBranch %[[#bb147:]]
229-
; CHECK: %[[#bb148:]] = OpLabel
230-
; CHECK: OpBranch %[[#bb147:]]
231-
; CHECK: %[[#bb147:]] = OpLabel
232-
; CHECK: OpBranch %[[#bb140:]]
233-
; CHECK: %[[#bb140:]] = OpLabel
237+
; CHECK: OpBranch %[[#bb143:]]
238+
; CHECK: %[[#bb143:]] = OpLabel
234239
; CHECK: OpReturnValue %[[#]]
235-
; CHECK: %[[#bb137:]] = OpLabel
236-
; CHECK: OpBranch %[[#bb136:]]
237-
; CHECK: %[[#bb134:]] = OpLabel
238-
; CHECK: OpBranch %[[#bb133:]]
239-
; CHECK: %[[#bb130:]] = OpLabel
240-
; CHECK: OpBranch %[[#bb129:]]
241-
; CHECK: %[[#bb122:]] = OpLabel
242-
; CHECK: OpBranch %[[#bb120:]]
243-
; CHECK: %[[#bb121:]] = OpLabel
244-
; CHECK: OpBranch %[[#bb120:]]
245-
; CHECK: %[[#bb109:]] = OpLabel
246-
; CHECK: OpBranch %[[#bb103:]]
240+
; CHECK: %[[#bb140:]] = OpLabel
241+
; CHECK: OpBranch %[[#bb139:]]
242+
; CHECK: %[[#bb138:]] = OpLabel
243+
; CHECK: OpBranch %[[#bb113:]]
244+
; CHECK: %[[#bb124:]] = OpLabel
245+
; CHECK: OpBranch %[[#bb122:]]
246+
; CHECK: %[[#bb123:]] = OpLabel
247+
; CHECK: OpBranch %[[#bb122:]]
248+
; CHECK: %[[#bb111:]] = OpLabel
249+
; CHECK: OpBranch %[[#bb105:]]
250+
; CHECK: %[[#bb104:]] = OpLabel
251+
; CHECK: OpBranch %[[#bb98:]]
247252
; CHECK: %[[#bb102:]] = OpLabel
248-
; CHECK: OpBranch %[[#bb96:]]
249-
; CHECK: %[[#bb100:]] = OpLabel
250-
; CHECK: OpBranch %[[#bb99:]]
253+
; CHECK: OpBranch %[[#bb101:]]
251254
; CHECK: OpFunctionEnd
252-
; CHECK: %[[#func_90:]] = OpFunction %[[#void:]] DontInline %[[#]]
253-
; CHECK: %[[#bb151:]] = OpLabel
255+
; CHECK: %[[#func_92:]] = OpFunction %[[#void:]] DontInline %[[#]]
256+
; CHECK: %[[#bb154:]] = OpLabel
254257
; CHECK: OpReturn
255258
; CHECK: OpFunctionEnd
256-
; CHECK: %[[#func_92:]] = OpFunction %[[#void:]] None %[[#]]
257-
; CHECK: %[[#bb152:]] = OpLabel
259+
; CHECK: %[[#func_94:]] = OpFunction %[[#void:]] None %[[#]]
260+
; CHECK: %[[#bb155:]] = OpLabel
258261
; CHECK: OpReturn
259262
; CHECK: OpFunctionEnd
260263

261-
262-
263264
target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
264265
target triple = "spirv-unknown-vulkan1.3-compute"
265266

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