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[GISel][AArch64] Changes based on comments
1 parent 9699955 commit eea6251

12 files changed

+116
-90
lines changed

‎llvm/include/llvm/Target/TargetSelectionDAG.td

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -959,7 +959,6 @@ class PatFrags<dag ops, list<dag> frags, code pred = [{}],
959959
list<dag> Fragments = frags;
960960
code PredicateCode = pred;
961961
code GISelPredicateCode = [{}];
962-
code GISelRegPredicateCode = [{}];
963962
code ImmediateCode = [{}];
964963
SDNodeXForm OperandTransform = xform;
965964

@@ -1062,7 +1061,9 @@ class OutPatFrag<dag ops, dag frag>
10621061
// PatLeaf's are pattern fragments that have no operands. This is just a helper
10631062
// to define immediates and other common things concisely.
10641063
class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
1065-
: PatFrag<(ops), frag, pred, xform>;
1064+
: PatFrag<(ops), frag, pred, xform> {
1065+
code GISelLeafPredicateCode = [{}];
1066+
}
10661067

10671068

10681069
// ImmLeaf is a pattern fragment with a constraint on the immediate. The

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -686,29 +686,33 @@ def top16Zero: PatLeaf<(i32 GPR32:$src), [{
686686
return Op.getValueType() == MVT::i32 &&
687687
CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(32, 16));
688688
}]> {
689-
let GISelRegPredicateCode = [{return isTop16Zero(MO); }];
689+
let GISelLeafPredicateCode = [{
690+
return (VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 16))); }];
690691
}
691692

692693
// top32Zero - answer true if the upper 32 bits of $src are 0, false otherwise
693694
def top32Zero: PatLeaf<(i64 GPR64:$src), [{
694695
return Op.getValueType() == MVT::i64 &&
695696
CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(64, 32));
696697
}]> {
697-
let GISelRegPredicateCode = [{ return isTop32Zero(MO); }];
698+
let GISelLeafPredicateCode = [{
699+
return (VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 32))); }];
698700
}
699701

700702
// topbitsallzero - Return true if all bits except the lowest bit are known zero
701703
def topbitsallzero32: PatLeaf<(i32 GPR32:$src), [{
702704
return Op.getValueType() == MVT::i32 &&
703705
CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(32, 31));
704706
}]> {
705-
let GISelRegPredicateCode = [{ return isTopBitsAllZero32(MO); }];
707+
let GISelLeafPredicateCode = [{
708+
return (VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 31))); }];
706709
}
707710
def topbitsallzero64: PatLeaf<(i64 GPR64:$src), [{
708711
return Op.getValueType() == MVT::i64 &&
709712
CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(64, 63));
710713
}]> {
711-
let GISelRegPredicateCode = [{ return isTopBitsAllZero64(MO); }];
714+
let GISelLeafPredicateCode = [{
715+
return (VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 63))); }];
712716
}
713717

714718
// Node definitions.

‎llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Lines changed: 0 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -7996,29 +7996,6 @@ bool AArch64InstructionSelector::isLoadStoreOfNumBytes(
79967996
return (*MI.memoperands_begin())->getSize() == NumBytes;
79977997
}
79987998

7999-
bool AArch64InstructionSelector::isTop16Zero(const MachineOperand &MO) const {
8000-
Register Reg = MO.getReg();
8001-
return VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 16));
8002-
}
8003-
8004-
// bool isTop32Zero(const MachineOperand &MO) const;
8005-
bool AArch64InstructionSelector::isTop32Zero(const MachineOperand &MO) const {
8006-
Register Reg = MO.getReg();
8007-
return VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 32));
8008-
}
8009-
8010-
bool AArch64InstructionSelector::isTopBitsAllZero32(
8011-
const MachineOperand &MO) const {
8012-
Register Reg = MO.getReg();
8013-
return VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 31));
8014-
}
8015-
8016-
bool AArch64InstructionSelector::isTopBitsAllZero64(
8017-
const MachineOperand &MO) const {
8018-
Register Reg = MO.getReg();
8019-
return VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 63));
8020-
}
8021-
80227999
bool AArch64InstructionSelector::isDef32(const MachineInstr &MI) const {
80238000
const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
80248001
if (MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() != 32)

‎llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td

Lines changed: 48 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -159,9 +159,19 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
159159
// CHECK-NEXT: };
160160

161161
// CHECK-LABEL: // PatFrag predicates.
162-
// CHECK-NEXT: bool MyTargetInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
162+
// CHECK-NEXT: enum {
163+
// CHECK-NEXT: GICXXPred_MO_Predicate_leaf = GICXXPred_Invalid + 1,
164+
// CHECK-NEXT: };
165+
166+
// CHECK-LABEL: bool MyTargetInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
163167
// CHECK-NEXT: const auto &Operands = State.RecordedOperands;
168+
// CHECK-NEXT: Register Reg = MO.getReg();
164169
// CHECK-NEXT: (void)Operands;
170+
// CHECK-NEXT: switch (PredicateID) {
171+
// CHECK-NEXT: case GICXXPred_MO_Predicate_leaf: {
172+
// CHECK-NEXT: return true;
173+
// CHECK-NEXT: }
174+
// CHECK-NEXT: }
165175
// CHECK-NEXT: llvm_unreachable("Unknown predicate");
166176
// CHECK-NEXT: return false;
167177
// CHECK-NEXT: }
@@ -518,12 +528,12 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
518528
// R00C-NEXT: GIR_EraseRootFromParent_Done,
519529
// R00C-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
520530
//
521-
// R00O-NEXT: GIM_Reject,
531+
// R00O: GIM_Reject,
522532
// R00O-NEXT: // Label [[GROUP_NUM]]: @[[GROUP]]
523533
// R00O-NEXT: GIM_Reject,
524534
// R00O: // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
525535
// R00O-NEXT: GIM_Reject,
526-
// R00O-NEXT: }; // Size: 1856 bytes
536+
// R00O-NEXT: }; // Size: 1878 bytes
527537

528538
def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, GPR32:$src4),
529539
[(set GPR32:$dst,
@@ -838,7 +848,7 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
838848
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
839849
// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src3
840850
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
841-
// NOOPT-NEXT: // GIR_Coverage, 28,
851+
// NOOPT-NEXT: // GIR_Coverage, 29,
842852
// NOOPT-NEXT: GIR_EraseRootFromParent_Done,
843853
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
844854

@@ -847,6 +857,35 @@ def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3),
847857
(mul (add GPR32:$src1, GPR32:$src2), GPR32:$src3))]>,
848858
Requires<[HasA]>;
849859

860+
//===- Test a simple pattern with a PatLeaf and a predicate. ---------===//
861+
//
862+
// NOOPT-NEXT: /* 882 */ GIM_Try, /*On fail goto*//*Label 13*/ GIMT_Encode4(924), // Rule ID 24 //
863+
// NOOPT-NEXT: /* 887 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
864+
// NOOPT-NEXT: /* 890 */ GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB),
865+
// NOOPT-NEXT: /* 894 */ // MIs[0] DstI[dst]
866+
// NOOPT-NEXT: /* 894 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
867+
// NOOPT-NEXT: /* 897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
868+
// NOOPT-NEXT: /* 901 */ // MIs[0] src1
869+
// NOOPT-NEXT: /* 901 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
870+
// NOOPT-NEXT: /* 904 */ GIM_CheckRegOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_leaf),
871+
// NOOPT-NEXT: /* 909 */ // MIs[0] src2
872+
// NOOPT-NEXT: /* 909 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
873+
// NOOPT-NEXT: /* 912 */ GIM_CheckRegOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_leaf),
874+
// NOOPT-NEXT: /* 917 */ // (sub:{ *:[i32] } GPR32:{ *:[i32] }<<P:Predicate_leaf>>:$src1, GPR32:{ *:[i32] }<<P:Predicate_leaf>>:$src2) => (INSN5:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)
875+
// NOOPT-NEXT: /* 917 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN5),
876+
// NOOPT-NEXT: /* 922 */ GIR_RootConstrainSelectedInstOperands,
877+
// NOOPT-NEXT: /* 923 */ // GIR_Coverage, 24,
878+
// NOOPT-NEXT: /* 923 */ GIR_Done,
879+
// NOOPT-NEXT: /* 924 */ // Label 13: @924
880+
881+
def leaf: PatLeaf<(i32 GPR32:$src), [{ return true; // C++ code }]> {
882+
let GISelLeafPredicateCode = [{ return true; }];
883+
}
884+
def INSN5 : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
885+
def : Pat<(sub leaf:$src1, leaf:$src2), (INSN5 GPR32:$src1, GPR32:$src2)>;
886+
887+
888+
850889
//===- Test a simple pattern with just a specific leaf immediate. ---------===//
851890
//
852891
// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]),
@@ -994,7 +1033,7 @@ def LOAD : I<(outs GPR32:$dst), (ins GPR32:$src1),
9941033
// NOOPT-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src)
9951034
// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD),
9961035
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
997-
// NOOPT-NEXT: // GIR_Coverage, 24,
1036+
// NOOPT-NEXT: // GIR_Coverage, 25,
9981037
// NOOPT-NEXT: GIR_Done,
9991038
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
10001039

@@ -1093,7 +1132,7 @@ def DOUBLE : I<(outs GPR32:$dst), (ins GPR32:$src), [(set GPR32:$dst, (add GPR32
10931132
// NOOPT-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$samename, i32:{ *:[i32] }:$othername) => (InsnWithSpeciallyNamedDef:{ *:[i32] } i32:{ *:[i32] }:$samename, i32:{ *:[i32] }:$othername)
10941133
// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::InsnWithSpeciallyNamedDef),
10951134
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
1096-
// NOOPT-NEXT: // GIR_Coverage, 25,
1135+
// NOOPT-NEXT: // GIR_Coverage, 26,
10971136
// NOOPT-NEXT: GIR_Done,
10981137
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
10991138

@@ -1116,7 +1155,7 @@ def : Pat<(add i32:$samename, i32:$othername),
11161155
// NOOPT-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (ADD:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
11171156
// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ADD),
11181157
// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands,
1119-
// NOOPT-NEXT: // GIR_Coverage, 26,
1158+
// NOOPT-NEXT: // GIR_Coverage, 27,
11201159
// NOOPT-NEXT: GIR_Done,
11211160
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
11221161

@@ -1167,7 +1206,7 @@ def MUL : I<(outs GPR32:$dst), (ins GPR32:$src2, GPR32:$src1),
11671206
// NOOPT-NEXT: // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$src1) => (COPY_TO_REGCLASS:{ *:[i32] } FPR32:{ *:[f32] }:$src1, GPR32:{ *:[i32] })
11681207
// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11691208
// NOOPT-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(MyTarget::GPR32RegClassID),
1170-
// NOOPT-NEXT: // GIR_Coverage, 27,
1209+
// NOOPT-NEXT: // GIR_Coverage, 28,
11711210
// NOOPT-NEXT: GIR_Done,
11721211
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
11731212

@@ -1216,5 +1255,5 @@ def BR : I<(outs), (ins unknown:$target),
12161255
[(br bb:$target)]>;
12171256

12181257
// NOOPT-NEXT: GIM_Reject,
1219-
// NOOPT-NEXT: }; // Size: 1459 bytes
1258+
// NOOPT-NEXT: }; // Size: 1501 bytes
12201259
// NOOPT-NEXT: return MatchTable0;

‎llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1293,19 +1293,21 @@ bool TreePredicateFn::hasGISelPredicateCode() const {
12931293
}
12941294

12951295
std::string TreePredicateFn::getGISelPredicateCode() const {
1296-
return std::string(
1297-
PatFragRec->getRecord()->getValueAsString("GISelPredicateCode"));
1296+
return PatFragRec->getRecord()->getValueAsString("GISelPredicateCode").str();
12981297
}
12991298

1300-
bool TreePredicateFn::hasGISelRegPredicateCode() const {
1301-
return !PatFragRec->getRecord()
1302-
->getValueAsString("GISelRegPredicateCode")
1303-
.empty();
1299+
bool TreePredicateFn::hasGISelLeafPredicateCode() const {
1300+
return (!PatFragRec->getRecord()
1301+
->getValueAsOptionalString("GISelLeafPredicateCode")
1302+
.value_or(std::string())
1303+
.empty());
13041304
}
13051305

1306-
std::string TreePredicateFn::getGISelRegPredicateCode() const {
1307-
return std::string(
1308-
PatFragRec->getRecord()->getValueAsString("GISelRegPredicateCode"));
1306+
std::string TreePredicateFn::getGISelLeafPredicateCode() const {
1307+
return PatFragRec->getRecord()
1308+
->getValueAsOptionalString("GISelLeafPredicateCode")
1309+
.value_or(std::string())
1310+
.str();
13091311
}
13101312

13111313
StringRef TreePredicateFn::getImmType() const {

‎llvm/utils/TableGen/Common/CodeGenDAGPatterns.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -592,8 +592,8 @@ class TreePredicateFn {
592592

593593
// If true, indicates that GlobalISel-based C++ code was supplied for checking
594594
// register operands.
595-
bool hasGISelRegPredicateCode() const;
596-
std::string getGISelRegPredicateCode() const;
595+
bool hasGISelLeafPredicateCode() const;
596+
std::string getGISelLeafPredicateCode() const;
597597

598598
private:
599599
bool hasPredCode() const;

‎llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ Error failUnsupported(const Twine &Reason) {
3333
std::string getEnumNameForPredicate(const TreePredicateFn &Predicate) {
3434
if (Predicate.hasGISelPredicateCode())
3535
return "GICXXPred_MI_" + Predicate.getFnName();
36-
else if (Predicate.hasGISelRegPredicateCode())
36+
if (Predicate.hasGISelLeafPredicateCode())
3737
return "GICXXPred_MO_" + Predicate.getFnName();
3838
return "GICXXPred_" + Predicate.getImmTypeIdentifier().str() + "_" +
3939
Predicate.getFnName();
@@ -1328,10 +1328,11 @@ void OperandImmPredicateMatcher::emitPredicateOpcodes(MatchTable &Table,
13281328
<< MatchTable::LineBreak;
13291329
}
13301330

1331-
//===- OperandRegPredicateMatcher -----------------------------------------===//
1331+
//===- OperandLeafPredicateMatcher
1332+
//-----------------------------------------===//
13321333

1333-
void OperandRegPredicateMatcher::emitPredicateOpcodes(MatchTable &Table,
1334-
RuleMatcher &Rule) const {
1334+
void OperandLeafPredicateMatcher::emitPredicateOpcodes(
1335+
MatchTable &Table, RuleMatcher &Rule) const {
13351336
Table << MatchTable::Opcode("GIM_CheckRegOperandPredicate")
13361337
<< MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID)
13371338
<< MatchTable::Comment("MO") << MatchTable::ULEB128Value(OpIdx)

‎llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -824,7 +824,7 @@ class PredicateMatcher {
824824
IPM_OneUse,
825825
IPM_GenericPredicate,
826826
IPM_MIFlags,
827-
OPM_RegPredicate,
827+
OPM_LeafPredicate,
828828
OPM_SameOperand,
829829
OPM_ComplexPattern,
830830
OPM_IntrinsicID,
@@ -1258,18 +1258,18 @@ class OperandImmPredicateMatcher : public OperandPredicateMatcher {
12581258

12591259
/// Generates code to check that this operand is a register whose value meets
12601260
/// the predicate.
1261-
class OperandRegPredicateMatcher : public OperandPredicateMatcher {
1261+
class OperandLeafPredicateMatcher : public OperandPredicateMatcher {
12621262
protected:
12631263
TreePredicateFn Predicate;
12641264

12651265
public:
1266-
OperandRegPredicateMatcher(unsigned InsnVarID, unsigned OpIdx,
1267-
const TreePredicateFn &Predicate)
1268-
: OperandPredicateMatcher(OPM_RegPredicate, InsnVarID, OpIdx),
1266+
OperandLeafPredicateMatcher(unsigned InsnVarID, unsigned OpIdx,
1267+
const TreePredicateFn &Predicate)
1268+
: OperandPredicateMatcher(OPM_LeafPredicate, InsnVarID, OpIdx),
12691269
Predicate(Predicate) {}
12701270

12711271
static bool classof(const PredicateMatcher *P) {
1272-
return P->getKind() == OPM_RegPredicate;
1272+
return P->getKind() == OPM_LeafPredicate;
12731273
}
12741274

12751275
void emitPredicateOpcodes(MatchTable &Table,

‎llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -182,7 +182,7 @@ void GlobalISelMatchTableExecutorEmitter::emitExecutorImpl(
182182
emitSubtargetFeatureBitsetImpl(OS, Rules);
183183
emitComplexPredicates(OS, ComplexOperandMatchers);
184184
emitMIPredicateFns(OS);
185-
emitRegPredicateFns(OS);
185+
emitLeafPredicateFns(OS);
186186
emitI64ImmPredicateFns(OS);
187187
emitAPFloatImmPredicateFns(OS);
188188
emitAPIntImmPredicateFns(OS);

‎llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.h

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -79,8 +79,8 @@ class GlobalISelMatchTableExecutorEmitter {
7979
raw_ostream &OS, StringRef TypeIdentifier, StringRef ArgType,
8080
StringRef ArgName, StringRef AdditionalArgs,
8181
StringRef AdditionalDeclarations, ArrayRef<PredicateObject> Predicates,
82-
std::function<StringRef(PredicateObject)> GetPredEnumName,
83-
std::function<StringRef(PredicateObject)> GetPredCode,
82+
llvm::function_ref<StringRef(PredicateObject)> GetPredEnumName,
83+
llvm::function_ref<StringRef(PredicateObject)> GetPredCode,
8484
StringRef Comment) {
8585
if (!Comment.empty())
8686
OS << "// " << Comment << "\n";
@@ -135,28 +135,28 @@ class GlobalISelMatchTableExecutorEmitter {
135135
void emitMIPredicateFnsImpl(
136136
raw_ostream &OS, StringRef AdditionalDecls,
137137
ArrayRef<PredicateObject> Predicates,
138-
std::function<StringRef(PredicateObject)> GetPredEnumName,
139-
std::function<StringRef(PredicateObject)> GetPredCode,
138+
llvm::function_ref<StringRef(PredicateObject)> GetPredEnumName,
139+
llvm::function_ref<StringRef(PredicateObject)> GetPredCode,
140140
StringRef Comment = "") {
141141
return emitCxxPredicateFns(
142142
OS, "MI", "const MachineInstr &", "MI", ", const MatcherState &State",
143143
AdditionalDecls, Predicates, GetPredEnumName, GetPredCode, Comment);
144144
}
145145

146146
/// Emits `testMOPredicate_MO`.
147-
/// @tparam PredicateObject An object representing a predicate to emit.
148-
/// @param OS Output stream.
149-
/// @param AdditionalDecls Additional C++ variable declarations.
150-
/// @param Predicates Predicates to emit.
151-
/// @param GetPredEnumName Returns an enum name for a given predicate.
152-
/// @param GetPredCode Returns the C++ code of a given predicate.
153-
/// @param Comment Optional comment for the enum declaration.
147+
/// \tparam PredicateObject An object representing a predicate to emit.
148+
/// \param OS Output stream.
149+
/// \param AdditionalDecls Additional C++ variable declarations.
150+
/// \param Predicates Predicates to emit.
151+
/// \param GetPredEnumName Returns an enum name for a given predicate.
152+
/// \param GetPredCode Returns the C++ code of a given predicate.
153+
/// \param Comment Optional comment for the enum declaration.
154154
template <typename PredicateObject>
155-
void emitRegPredicateFnsImpl(
155+
void emitLeafPredicateFnsImpl(
156156
raw_ostream &OS, StringRef AdditionalDecls,
157157
ArrayRef<PredicateObject> Predicates,
158-
std::function<StringRef(PredicateObject)> GetPredEnumName,
159-
std::function<StringRef(PredicateObject)> GetPredCode,
158+
llvm::function_ref<StringRef(PredicateObject)> GetPredEnumName,
159+
llvm::function_ref<StringRef(PredicateObject)> GetPredCode,
160160
StringRef Comment = "") {
161161
return emitCxxPredicateFns(
162162
OS, "MO", "const MachineOperand &", "MO", ", const MatcherState &State",
@@ -180,8 +180,8 @@ class GlobalISelMatchTableExecutorEmitter {
180180
void emitImmPredicateFnsImpl(
181181
raw_ostream &OS, StringRef TypeIdentifier, StringRef ArgType,
182182
ArrayRef<PredicateObject> Predicates,
183-
std::function<StringRef(PredicateObject)> GetPredEnumName,
184-
std::function<StringRef(PredicateObject)> GetPredCode,
183+
llvm::function_ref<StringRef(PredicateObject)> GetPredEnumName,
184+
llvm::function_ref<StringRef(PredicateObject)> GetPredCode,
185185
StringRef Comment = "") {
186186
return emitCxxPredicateFns(OS, TypeIdentifier, ArgType, "Imm", "", "",
187187
Predicates, GetPredEnumName, GetPredCode,
@@ -209,9 +209,9 @@ class GlobalISelMatchTableExecutorEmitter {
209209
/// Note: `emitMIPredicateFnsImpl` can be used to do most of the work.
210210
virtual void emitMIPredicateFns(raw_ostream &OS) = 0;
211211

212-
/// Emit the `testRegPredicate` function
213-
/// Note `emitRegPredicateFnsImpl` can be used to do most of the work.
214-
virtual void emitRegPredicateFns(raw_ostream &OS) = 0;
212+
/// Emit the `testLeafPredicate` function
213+
/// Note `emitLeafPredicateFnsImpl` can be used to do most of the work.
214+
virtual void emitLeafPredicateFns(raw_ostream &OS) = 0;
215215

216216
/// Emit the `testImmPredicate_I64` function.
217217
/// Note: `emitImmPredicateFnsImpl` can be used to do most of the work.

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