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[NFC][clang] Split clang/lib/CodeGen/CGBuiltin.cpp into target-specific files
clang/lib/CodeGen/CGBuiltin.cpp is over 1MB long (>23k LoC), and can take minutes to recompile (depending on compiler and host system) when modified, and 5 seconds for clangd to update for every edit. Splitting this file was discussed in this thread: https://discourse.llvm.org/t/splitting-clang-s-cgbuiltin-cpp-over-23k-lines-long-takes-1min-to-compile/ and the idea has received a number of +1 votes, hence this change.
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‎clang/lib/CodeGen/BuiltinTargets/AArch64.cpp

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‎clang/lib/CodeGen/BuiltinTargets/AMDGPU.cpp

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‎clang/lib/CodeGen/BuiltinTargets/Hexagon.cpp

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//===------ Hexagon.cpp - Emit LLVM Code for builtins ---------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This contains code to emit Builtin calls as LLVM code.
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//
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//===----------------------------------------------------------------------===//
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#include "ABIInfo.h"
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#include "CodeGenFunction.h"
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#include "TargetInfo.h"
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#include "clang/Basic/TargetBuiltins.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/IntrinsicsHexagon.h"
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using namespace clang;
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using namespace CodeGen;
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using namespace llvm;
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static std::pair<Intrinsic::ID, unsigned>
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getIntrinsicForHexagonNonClangBuiltin(unsigned BuiltinID) {
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struct Info {
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unsigned BuiltinID;
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Intrinsic::ID IntrinsicID;
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unsigned VecLen;
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};
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static Info Infos[] = {
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#define CUSTOM_BUILTIN_MAPPING(x, s) \
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{Hexagon::BI__builtin_HEXAGON_##x, Intrinsic::hexagon_##x, s},
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CUSTOM_BUILTIN_MAPPING(L2_loadrub_pci, 0) CUSTOM_BUILTIN_MAPPING(
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L2_loadrb_pci,
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0) CUSTOM_BUILTIN_MAPPING(L2_loadruh_pci,
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0) CUSTOM_BUILTIN_MAPPING(L2_loadrh_pci, 0)
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CUSTOM_BUILTIN_MAPPING(L2_loadri_pci, 0) CUSTOM_BUILTIN_MAPPING(
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L2_loadrd_pci, 0) CUSTOM_BUILTIN_MAPPING(L2_loadrub_pcr, 0)
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CUSTOM_BUILTIN_MAPPING(L2_loadrb_pcr, 0) CUSTOM_BUILTIN_MAPPING(
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L2_loadruh_pcr, 0) CUSTOM_BUILTIN_MAPPING(L2_loadrh_pcr, 0)
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CUSTOM_BUILTIN_MAPPING(
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L2_loadri_pcr, 0) CUSTOM_BUILTIN_MAPPING(L2_loadrd_pcr, 0)
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CUSTOM_BUILTIN_MAPPING(
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S2_storerb_pci,
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0) CUSTOM_BUILTIN_MAPPING(S2_storerh_pci, 0)
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CUSTOM_BUILTIN_MAPPING(S2_storerf_pci, 0)
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CUSTOM_BUILTIN_MAPPING(S2_storeri_pci, 0)
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CUSTOM_BUILTIN_MAPPING(S2_storerd_pci, 0)
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CUSTOM_BUILTIN_MAPPING(S2_storerb_pcr, 0)
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CUSTOM_BUILTIN_MAPPING(S2_storerh_pcr,
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0)
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CUSTOM_BUILTIN_MAPPING(
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S2_storerf_pcr, 0)
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CUSTOM_BUILTIN_MAPPING(
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S2_storeri_pcr, 0)
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CUSTOM_BUILTIN_MAPPING(
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S2_storerd_pcr, 0)
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// Legacy builtins that take a vector in place of a vector predicate.
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CUSTOM_BUILTIN_MAPPING(V6_vmaskedstoreq, 64) CUSTOM_BUILTIN_MAPPING(
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V6_vmaskedstorenq, 64) CUSTOM_BUILTIN_MAPPING(V6_vmaskedstorentq, 64)
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CUSTOM_BUILTIN_MAPPING(V6_vmaskedstorentnq, 64)
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CUSTOM_BUILTIN_MAPPING(V6_vmaskedstoreq_128B, 128)
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CUSTOM_BUILTIN_MAPPING(V6_vmaskedstorenq_128B, 128)
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CUSTOM_BUILTIN_MAPPING(V6_vmaskedstorentq_128B, 128)
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CUSTOM_BUILTIN_MAPPING(V6_vmaskedstorentnq_128B, 128)
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#include "clang/Basic/BuiltinsHexagonMapCustomDep.def"
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#undef CUSTOM_BUILTIN_MAPPING
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};
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auto CmpInfo = [](Info A, Info B) { return A.BuiltinID < B.BuiltinID; };
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static const bool SortOnce = (llvm::sort(Infos, CmpInfo), true);
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(void)SortOnce;
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const Info *F = llvm::lower_bound(Infos, Info{BuiltinID, 0, 0}, CmpInfo);
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if (F == std::end(Infos) || F->BuiltinID != BuiltinID)
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return {Intrinsic::not_intrinsic, 0};
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return {F->IntrinsicID, F->VecLen};
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}
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Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID,
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const CallExpr *E) {
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Intrinsic::ID ID;
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unsigned VecLen;
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std::tie(ID, VecLen) = getIntrinsicForHexagonNonClangBuiltin(BuiltinID);
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auto MakeCircOp = [this, E](unsigned IntID, bool IsLoad) {
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// The base pointer is passed by address, so it needs to be loaded.
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Address A = EmitPointerWithAlignment(E->getArg(0));
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Address BP = Address(A.emitRawPointer(*this), Int8PtrTy, A.getAlignment());
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llvm::Value *Base = Builder.CreateLoad(BP);
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// The treatment of both loads and stores is the same: the arguments for
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// the builtin are the same as the arguments for the intrinsic.
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// Load:
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// builtin(Base, Inc, Mod, Start) -> intr(Base, Inc, Mod, Start)
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// builtin(Base, Mod, Start) -> intr(Base, Mod, Start)
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// Store:
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// builtin(Base, Inc, Mod, Val, Start) -> intr(Base, Inc, Mod, Val, Start)
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// builtin(Base, Mod, Val, Start) -> intr(Base, Mod, Val, Start)
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SmallVector<llvm::Value *, 5> Ops = {Base};
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for (unsigned i = 1, e = E->getNumArgs(); i != e; ++i)
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Ops.push_back(EmitScalarExpr(E->getArg(i)));
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llvm::Value *Result = Builder.CreateCall(CGM.getIntrinsic(IntID), Ops);
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// The load intrinsics generate two results (Value, NewBase), stores
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// generate one (NewBase). The new base address needs to be stored.
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llvm::Value *NewBase =
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IsLoad ? Builder.CreateExtractValue(Result, 1) : Result;
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llvm::Value *LV = EmitScalarExpr(E->getArg(0));
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Address Dest = EmitPointerWithAlignment(E->getArg(0));
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llvm::Value *RetVal =
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Builder.CreateAlignedStore(NewBase, LV, Dest.getAlignment());
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if (IsLoad)
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RetVal = Builder.CreateExtractValue(Result, 0);
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return RetVal;
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};
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// Handle the conversion of bit-reverse load intrinsics to bit code.
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// The intrinsic call after this function only reads from memory and the
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// write to memory is dealt by the store instruction.
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auto MakeBrevLd = [this, E](unsigned IntID, llvm::Type *DestTy) {
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// The intrinsic generates one result, which is the new value for the base
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// pointer. It needs to be returned. The result of the load instruction is
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// passed to intrinsic by address, so the value needs to be stored.
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llvm::Value *BaseAddress = EmitScalarExpr(E->getArg(0));
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// Expressions like &(*pt++) will be incremented per evaluation.
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// EmitPointerWithAlignment and EmitScalarExpr evaluates the expression
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// per call.
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Address DestAddr = EmitPointerWithAlignment(E->getArg(1));
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DestAddr = DestAddr.withElementType(Int8Ty);
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llvm::Value *DestAddress = DestAddr.emitRawPointer(*this);
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// Operands are Base, Dest, Modifier.
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// The intrinsic format in LLVM IR is defined as
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// { ValueType, i8* } (i8*, i32).
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llvm::Value *Result = Builder.CreateCall(
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CGM.getIntrinsic(IntID), {BaseAddress, EmitScalarExpr(E->getArg(2))});
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// The value needs to be stored as the variable is passed by reference.
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llvm::Value *DestVal = Builder.CreateExtractValue(Result, 0);
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// The store needs to be truncated to fit the destination type.
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// While i32 and i64 are natively supported on Hexagon, i8 and i16 needs
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// to be handled with stores of respective destination type.
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DestVal = Builder.CreateTrunc(DestVal, DestTy);
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Builder.CreateAlignedStore(DestVal, DestAddress, DestAddr.getAlignment());
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// The updated value of the base pointer is returned.
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return Builder.CreateExtractValue(Result, 1);
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};
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auto V2Q = [this, VecLen](llvm::Value *Vec) {
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Intrinsic::ID ID = VecLen == 128 ? Intrinsic::hexagon_V6_vandvrt_128B
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: Intrinsic::hexagon_V6_vandvrt;
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return Builder.CreateCall(CGM.getIntrinsic(ID),
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{Vec, Builder.getInt32(-1)});
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};
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auto Q2V = [this, VecLen](llvm::Value *Pred) {
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Intrinsic::ID ID = VecLen == 128 ? Intrinsic::hexagon_V6_vandqrt_128B
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: Intrinsic::hexagon_V6_vandqrt;
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return Builder.CreateCall(CGM.getIntrinsic(ID),
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{Pred, Builder.getInt32(-1)});
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};
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switch (BuiltinID) {
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// These intrinsics return a tuple {Vector, VectorPred} in LLVM IR,
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// and the corresponding C/C++ builtins use loads/stores to update
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// the predicate.
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case Hexagon::BI__builtin_HEXAGON_V6_vaddcarry:
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case Hexagon::BI__builtin_HEXAGON_V6_vaddcarry_128B:
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case Hexagon::BI__builtin_HEXAGON_V6_vsubcarry:
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case Hexagon::BI__builtin_HEXAGON_V6_vsubcarry_128B: {
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// Get the type from the 0-th argument.
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llvm::Type *VecType = ConvertType(E->getArg(0)->getType());
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Address PredAddr =
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EmitPointerWithAlignment(E->getArg(2)).withElementType(VecType);
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llvm::Value *PredIn = V2Q(Builder.CreateLoad(PredAddr));
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llvm::Value *Result = Builder.CreateCall(
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CGM.getIntrinsic(ID),
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{EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1)), PredIn});
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llvm::Value *PredOut = Builder.CreateExtractValue(Result, 1);
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Builder.CreateAlignedStore(Q2V(PredOut), PredAddr.emitRawPointer(*this),
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PredAddr.getAlignment());
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return Builder.CreateExtractValue(Result, 0);
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}
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// These are identical to the builtins above, except they don't consume
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// input carry, only generate carry-out. Since they still produce two
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// outputs, generate the store of the predicate, but no load.
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case Hexagon::BI__builtin_HEXAGON_V6_vaddcarryo:
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case Hexagon::BI__builtin_HEXAGON_V6_vaddcarryo_128B:
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case Hexagon::BI__builtin_HEXAGON_V6_vsubcarryo:
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case Hexagon::BI__builtin_HEXAGON_V6_vsubcarryo_128B: {
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// Get the type from the 0-th argument.
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llvm::Type *VecType = ConvertType(E->getArg(0)->getType());
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Address PredAddr =
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EmitPointerWithAlignment(E->getArg(2)).withElementType(VecType);
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llvm::Value *Result = Builder.CreateCall(
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CGM.getIntrinsic(ID),
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{EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1))});
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llvm::Value *PredOut = Builder.CreateExtractValue(Result, 1);
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Builder.CreateAlignedStore(Q2V(PredOut), PredAddr.emitRawPointer(*this),
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PredAddr.getAlignment());
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return Builder.CreateExtractValue(Result, 0);
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}
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case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstoreq:
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case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstorenq:
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case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstorentq:
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case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstorentnq:
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case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstoreq_128B:
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case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstorenq_128B:
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case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstorentq_128B:
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case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstorentnq_128B: {
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SmallVector<llvm::Value *, 4> Ops;
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const Expr *PredOp = E->getArg(0);
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// There will be an implicit cast to a boolean vector. Strip it.
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if (auto *Cast = dyn_cast<ImplicitCastExpr>(PredOp)) {
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if (Cast->getCastKind() == CK_BitCast)
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PredOp = Cast->getSubExpr();
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Ops.push_back(V2Q(EmitScalarExpr(PredOp)));
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}
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for (int i = 1, e = E->getNumArgs(); i != e; ++i)
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Ops.push_back(EmitScalarExpr(E->getArg(i)));
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return Builder.CreateCall(CGM.getIntrinsic(ID), Ops);
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}
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case Hexagon::BI__builtin_HEXAGON_L2_loadrub_pci:
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case Hexagon::BI__builtin_HEXAGON_L2_loadrb_pci:
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case Hexagon::BI__builtin_HEXAGON_L2_loadruh_pci:
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case Hexagon::BI__builtin_HEXAGON_L2_loadrh_pci:
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case Hexagon::BI__builtin_HEXAGON_L2_loadri_pci:
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case Hexagon::BI__builtin_HEXAGON_L2_loadrd_pci:
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case Hexagon::BI__builtin_HEXAGON_L2_loadrub_pcr:
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case Hexagon::BI__builtin_HEXAGON_L2_loadrb_pcr:
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case Hexagon::BI__builtin_HEXAGON_L2_loadruh_pcr:
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case Hexagon::BI__builtin_HEXAGON_L2_loadrh_pcr:
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case Hexagon::BI__builtin_HEXAGON_L2_loadri_pcr:
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case Hexagon::BI__builtin_HEXAGON_L2_loadrd_pcr:
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return MakeCircOp(ID, /*IsLoad=*/true);
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case Hexagon::BI__builtin_HEXAGON_S2_storerb_pci:
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case Hexagon::BI__builtin_HEXAGON_S2_storerh_pci:
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case Hexagon::BI__builtin_HEXAGON_S2_storerf_pci:
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case Hexagon::BI__builtin_HEXAGON_S2_storeri_pci:
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case Hexagon::BI__builtin_HEXAGON_S2_storerd_pci:
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case Hexagon::BI__builtin_HEXAGON_S2_storerb_pcr:
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case Hexagon::BI__builtin_HEXAGON_S2_storerh_pcr:
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case Hexagon::BI__builtin_HEXAGON_S2_storerf_pcr:
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case Hexagon::BI__builtin_HEXAGON_S2_storeri_pcr:
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case Hexagon::BI__builtin_HEXAGON_S2_storerd_pcr:
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return MakeCircOp(ID, /*IsLoad=*/false);
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case Hexagon::BI__builtin_brev_ldub:
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return MakeBrevLd(Intrinsic::hexagon_L2_loadrub_pbr, Int8Ty);
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case Hexagon::BI__builtin_brev_ldb:
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return MakeBrevLd(Intrinsic::hexagon_L2_loadrb_pbr, Int8Ty);
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case Hexagon::BI__builtin_brev_lduh:
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return MakeBrevLd(Intrinsic::hexagon_L2_loadruh_pbr, Int16Ty);
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case Hexagon::BI__builtin_brev_ldh:
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return MakeBrevLd(Intrinsic::hexagon_L2_loadrh_pbr, Int16Ty);
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case Hexagon::BI__builtin_brev_ldw:
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return MakeBrevLd(Intrinsic::hexagon_L2_loadri_pbr, Int32Ty);
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case Hexagon::BI__builtin_brev_ldd:
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return MakeBrevLd(Intrinsic::hexagon_L2_loadrd_pbr, Int64Ty);
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} // switch
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return nullptr;
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}

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