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nashermnasherm
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Clang formatting
Change-Id: Ibf1ffab27184a12a5d0fdab2ec7af437192552b5
1 parent 02ac9dd commit eee909e

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5 files changed

+16
-17
lines changed

5 files changed

+16
-17
lines changed

‎llvm/lib/Target/ARM/ARMFeatures.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -372,10 +372,10 @@ def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
372372
def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Prefers32BitThumb", "true",
373373
"Prefer 32-bit Thumb instrs">;
374374

375-
def FeaturePrefBranchAlign32 : SubtargetFeature<"loop-align", "PrefBranchLogAlignment","2",
375+
def FeaturePreferBranchAlign32 : SubtargetFeature<"branch-align", "PreferBranchLogAlignment","2",
376376
"Prefer 32-bit alignment for branch targets">;
377377

378-
def FeaturePrefBranchAlign64 : SubtargetFeature<"loop-align-64", "PrefBranchLogAlignment","3",
378+
def FeaturePreferBranchAlign64 : SubtargetFeature<"branch-align-64", "PreferBranchLogAlignment","3",
379379
"Prefer 64-bit alignment for branch targets">;
380380

381381
def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "4",

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1635,10 +1635,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
16351635
// Prefer likely predicted branches to selects on out-of-order cores.
16361636
PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
16371637

1638-
setPrefLoopAlignment(
1639-
Align(1ULL << Subtarget->getPrefBranchLogAlignment()));
1638+
setPrefLoopAlignment(Align(1ULL << Subtarget->getPreferBranchLogAlignment()));
16401639
setPrefFunctionAlignment(
1641-
Align(1ULL << Subtarget->getPrefBranchLogAlignment()));
1640+
Align(1ULL << Subtarget->getPreferBranchLogAlignment()));
16421641

16431642
setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
16441643
}

‎llvm/lib/Target/ARM/ARMProcessors.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -324,7 +324,7 @@ def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
324324

325325
def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m,
326326
ProcM3,
327-
FeaturePrefBranchAlign32,
327+
FeaturePreferBranchAlign32,
328328
FeatureUseMISched,
329329
FeatureHasNoBranchPredictor]>;
330330

@@ -335,7 +335,7 @@ def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m,
335335

336336
def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em,
337337
FeatureVFP4_D16_SP,
338-
FeaturePrefBranchAlign32,
338+
FeaturePreferBranchAlign32,
339339
FeatureHasSlowFPVMLx,
340340
FeatureHasSlowFPVFMx,
341341
FeatureUseMISched,
@@ -344,7 +344,7 @@ def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em,
344344
def : ProcessorModel<"cortex-m7", CortexM7Model, [ARMv7em,
345345
ProcM7,
346346
FeatureFPARMv8_D16,
347-
FeaturePrefBranchAlign64,
347+
FeaturePreferBranchAlign64,
348348
FeatureUseMIPipeliner,
349349
FeatureUseMISched]>;
350350

@@ -355,7 +355,7 @@ def : ProcNoItin<"cortex-m23", [ARMv8mBaseline,
355355
def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline,
356356
FeatureDSP,
357357
FeatureFPARMv8_D16_SP,
358-
FeaturePrefBranchAlign32,
358+
FeaturePreferBranchAlign32,
359359
FeatureHasSlowFPVMLx,
360360
FeatureHasSlowFPVFMx,
361361
FeatureUseMISched,
@@ -365,7 +365,7 @@ def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline,
365365
def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline,
366366
FeatureDSP,
367367
FeatureFPARMv8_D16_SP,
368-
FeaturePrefBranchAlign32,
368+
FeaturePreferBranchAlign32,
369369
FeatureHasSlowFPVMLx,
370370
FeatureHasSlowFPVFMx,
371371
FeatureUseMISched,
@@ -377,7 +377,7 @@ def : ProcessorModel<"cortex-m55", CortexM55Model, [ARMv81mMainline,
377377
FeatureFPARMv8_D16,
378378
FeatureUseMISched,
379379
FeatureHasNoBranchPredictor,
380-
FeaturePrefBranchAlign32,
380+
FeaturePreferBranchAlign32,
381381
FeatureHasSlowFPVMLx,
382382
HasMVEFloatOps,
383383
FeatureFixCMSE_CVE_2021_35465]>;
@@ -386,7 +386,7 @@ def : ProcessorModel<"cortex-m85", CortexM85Model, [ARMv81mMainline,
386386
FeatureDSP,
387387
FeatureFPARMv8_D16,
388388
FeaturePACBTI,
389-
FeaturePrefBranchAlign64,
389+
FeaturePreferBranchAlign64,
390390
FeatureUseMISched,
391391
HasMVEFloatOps]>;
392392

@@ -396,7 +396,7 @@ def : ProcessorModel<"cortex-m52", CortexM55Model, [ARMv81mMainline,
396396
FeatureHasNoBranchPredictor,
397397
FeaturePACBTI,
398398
FeatureUseMISched,
399-
FeaturePrefBranchAlign32,
399+
FeaturePreferBranchAlign32,
400400
FeatureHasSlowFPVMLx,
401401
FeatureMVEVectorCostFactor1,
402402
HasMVEFloatOps]>;

‎llvm/lib/Target/ARM/ARMSubtarget.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -302,7 +302,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
302302
LdStMultipleTiming = SingleIssuePlusExtras;
303303
MaxInterleaveFactor = 4;
304304
if (!isThumb())
305-
PrefBranchLogAlignment = 3;
305+
PreferBranchLogAlignment = 3;
306306
break;
307307
case Kryo:
308308
break;

‎llvm/lib/Target/ARM/ARMSubtarget.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -133,7 +133,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
133133
int PreISelOperandLatencyAdjustment = 2;
134134

135135
/// What alignment is preferred for loop bodies and functions, in log2(bytes).
136-
unsigned PrefBranchLogAlignment = 0;
136+
unsigned PreferBranchLogAlignment = 0;
137137

138138
/// The cost factor for MVE instructions, representing the multiple beats an
139139
// instruction can take. The default is 2, (set in initSubtargetFeatures so
@@ -476,8 +476,8 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
476476
return isROPI() || !isTargetELF();
477477
}
478478

479-
unsigned getPrefBranchLogAlignment() const {
480-
return PrefBranchLogAlignment;
479+
unsigned getPreferBranchLogAlignment() const {
480+
return PreferBranchLogAlignment;
481481
}
482482

483483
unsigned

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