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[AArch64] Assembly support for the Checked Pointer Arithmetic Extension (#73777)
This introduces assembly support for the Checked Pointer Arithmetic Extension (FEAT_CPA), annouced as part of the Armv9.5-A architecture version. The changes include: * New subtarget feature for FEAT_CPA * New scalar instruction for pointer arithmetic * ADDPT, SUBPT, MADDPT, and MSUBPT * New SVE instructions for pointer arithmetic * ADDPT (vectors, predicated), ADDPT (vectors, unpredicated) * SUBPT (vectors, predicated), SUBPT (vectors, unpredicated) * MADPT and MLAPT * New ID_AA64ISAR3_EL1 system register Mode details about the extension can be found at: * https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023 * https://developer.arm.com/documentation/ddi0602/2023-09/ Co-authored-by: Rodolfo Wottrich <[email protected]>
1 parent 3246a32 commit eef8e1d

19 files changed

+336
-7
lines changed

‎clang/test/Driver/aarch64-v95a.c

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,3 +13,8 @@
1313
// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s
1414
// GENERICV95A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.5a"
1515

16+
// ===== Features supported on aarch64 =====
17+
18+
// RUN: %clang -target aarch64 -march=armv9.5a+cpa -### -c %s 2>&1 | FileCheck -check-prefix=V95A-CPA %s
19+
// RUN: %clang -target aarch64 -march=armv9.5-a+cpa -### -c %s 2>&1 | FileCheck -check-prefix=V95A-CPA %s
20+
// V95A-CPA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.5a" "-target-feature" "+cpa"

‎llvm/include/llvm/TargetParser/AArch64TargetParser.h

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -173,6 +173,7 @@ enum ArchExtKind : unsigned {
173173
AEK_SMEF8F16 = 69, // FEAT_SME_F8F16
174174
AEK_SMEF8F32 = 70, // FEAT_SME_F8F32
175175
AEK_SMEFA64 = 71, // FEAT_SME_FA64
176+
AEK_CPA = 72, // FEAT_CPA
176177
AEK_NUM_EXTENSIONS
177178
};
178179
using ExtensionBitset = Bitset<AEK_NUM_EXTENSIONS>;
@@ -295,6 +296,7 @@ inline constexpr ExtensionInfo Extensions[] = {
295296
{"sme-f8f16", AArch64::AEK_SMEF8F16, "+sme-f8f16", "-sme-f8f16", FEAT_INIT, "+sme2,+fp8", 0},
296297
{"sme-f8f32", AArch64::AEK_SMEF8F32, "+sme-f8f32", "-sme-f8f32", FEAT_INIT, "+sme2,+fp8", 0},
297298
{"sme-fa64", AArch64::AEK_SMEFA64, "+sme-fa64", "-sme-fa64", FEAT_INIT, "", 0},
299+
{"cpa", AArch64::AEK_CPA, "+cpa", "-cpa", FEAT_INIT, "", 0},
298300
// Special cases
299301
{"none", AArch64::AEK_NONE, {}, {}, FEAT_INIT, "", ExtensionInfo::MaxFMVPriority},
300302
};
@@ -378,7 +380,8 @@ inline constexpr ArchInfo ARMV9_3A = { VersionTuple{9, 3}, AProfile, "armv9.3-a
378380
AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))};
379381
inline constexpr ArchInfo ARMV9_4A = { VersionTuple{9, 4}, AProfile, "armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts |
380382
AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC, AArch64::AEK_RASv2}))};
381-
inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile, "armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts)};
383+
inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile, "armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts |
384+
AArch64::ExtensionBitset({AArch64::AEK_CPA}))};
382385
// For v8-R, we do not enable crypto and align with GCC that enables a more minimal set of optional architecture extensions.
383386
inline constexpr ArchInfo ARMV8R = { VersionTuple{8, 0}, RProfile, "armv8-r", "+v8r", (ARMV8_5A.DefaultExts |
384387
AArch64::ExtensionBitset({AArch64::AEK_SSBS,

‎llvm/lib/Target/AArch64/AArch64.td

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -622,6 +622,9 @@ def FeatureLdpAlignedOnly : SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
622622
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only", "HasStpAlignedOnly",
623623
"true", "In order to emit stp, first check if the store will be aligned to 2 * element_size">;
624624

625+
def FeatureCPA : SubtargetFeature<"cpa", "HasCPA", "true",
626+
"Enable ARMv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
627+
625628
//===----------------------------------------------------------------------===//
626629
// Architectures.
627630
//
@@ -692,7 +695,7 @@ def HasV9_4aOps : SubtargetFeature<
692695

693696
def HasV9_5aOps : SubtargetFeature<
694697
"v9.5a", "HasV9_5aOps", "true", "Support ARM v9.5a instructions",
695-
[HasV9_4aOps]>;
698+
[HasV9_4aOps, FeatureCPA]>;
696699

697700
def HasV8_0rOps : SubtargetFeature<
698701
"v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12446,6 +12446,58 @@ class SystemPXtI<bit L, string asm> :
1244612446
BaseSYSPEncoding<L, asm, "\t$op1, $Cn, $Cm, $op2, $Rt", (outs),
1244712447
(ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XSeqPairClassOperand:$Rt)>;
1244812448

12449+
//----------------------------------------------------------------------------
12450+
// 2023 Armv9.5 Extensions
12451+
//----------------------------------------------------------------------------
12452+
12453+
//---
12454+
// Checked Pointer Arithmetic (FEAT_CPA)
12455+
//---
12456+
12457+
def LSLImm3ShiftOperand : AsmOperandClass {
12458+
let SuperClasses = [ExtendOperandLSL64];
12459+
let Name = "LSLImm3Shift";
12460+
let RenderMethod = "addLSLImm3ShifterOperands";
12461+
let DiagnosticType = "AddSubLSLImm3ShiftLarge";
12462+
}
12463+
12464+
def lsl_imm3_shift_operand : Operand<i32> {
12465+
let PrintMethod = "printShifter";
12466+
let ParserMatchClass = LSLImm3ShiftOperand;
12467+
}
12468+
12469+
// Base CPA scalar add/subtract with lsl #imm3 shift
12470+
class BaseAddSubCPA<bit isSub, string asm> : I<(outs GPR64sp:$Rd),
12471+
(ins GPR64sp:$Rn, GPR64:$Rm, lsl_imm3_shift_operand:$shift_imm),
12472+
asm, "\t$Rd, $Rn, $Rm$shift_imm", "", []>, Sched<[]> {
12473+
bits<5> Rd;
12474+
bits<5> Rn;
12475+
bits<5> Rm;
12476+
bits<3> shift_imm;
12477+
let Inst{31} = 0b1;
12478+
let Inst{30} = isSub;
12479+
let Inst{29-21} = 0b011010000;
12480+
let Inst{20-16} = Rm;
12481+
let Inst{15-13} = 0b001;
12482+
let Inst{12-10} = shift_imm;
12483+
let Inst{9-5} = Rn;
12484+
let Inst{4-0} = Rd;
12485+
}
12486+
12487+
// Alias for CPA scalar add/subtract with no shift
12488+
class AddSubCPAAlias<string asm, Instruction inst>
12489+
: InstAlias<asm#"\t$Rd, $Rn, $Rm",
12490+
(inst GPR64sp:$Rd, GPR64sp:$Rn, GPR64:$Rm, 0)>;
12491+
12492+
multiclass AddSubCPA<bit isSub, string asm> {
12493+
def _shift : BaseAddSubCPA<isSub, asm>;
12494+
def _noshift : AddSubCPAAlias<asm, !cast<Instruction>(NAME#"_shift")>;
12495+
}
12496+
12497+
class MulAccumCPA<bit isSub, string asm>
12498+
: BaseMulAccum<isSub, 0b011, GPR64, GPR64, asm, []>, Sched<[]> {
12499+
let Inst{31} = 0b1;
12500+
}
1244912501

1245012502
//----------------------------------------------------------------------------
1245112503
// Allow the size specifier tokens to be upper case, not just lower.

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -289,6 +289,8 @@ def HasCHK : Predicate<"Subtarget->hasCHK()">,
289289
AssemblerPredicateWithAll<(all_of FeatureCHK), "chk">;
290290
def HasGCS : Predicate<"Subtarget->hasGCS()">,
291291
AssemblerPredicateWithAll<(all_of FeatureGCS), "gcs">;
292+
def HasCPA : Predicate<"Subtarget->hasCPA()">,
293+
AssemblerPredicateWithAll<(all_of FeatureCPA), "cpa">;
292294
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
293295
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
294296
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
@@ -9367,6 +9369,10 @@ let Predicates = [HasD128] in {
93679369
}
93689370
}
93699371

9372+
//===----------------------------===//
9373+
// 2023 Architecture Extensions:
9374+
//===----------------------------===//
9375+
93709376
let Predicates = [HasFP8] in {
93719377
defm F1CVTL : SIMDMixedTwoVectorFP8<0b00, "f1cvtl">;
93729378
defm F2CVTL : SIMDMixedTwoVectorFP8<0b01, "f2cvtl">;
@@ -9408,6 +9414,19 @@ let Predicates = [HasFP8DOT4] in {
94089414
defm FDOT : SIMDThreeSameVectorDOT4<"fdot">;
94099415
} // End let Predicates = [HasFP8DOT4]
94109416

9417+
//===----------------------------------------------------------------------===//
9418+
// Checked Pointer Arithmetic (FEAT_CPA)
9419+
//===----------------------------------------------------------------------===//
9420+
let Predicates = [HasCPA] in {
9421+
// Scalar add/subtract
9422+
defm ADDPT : AddSubCPA<0, "addpt">;
9423+
defm SUBPT : AddSubCPA<1, "subpt">;
9424+
9425+
// Scalar multiply-add/subtract
9426+
def MADDPT : MulAccumCPA<0, "maddpt">;
9427+
def MSUBPT : MulAccumCPA<1, "msubpt">;
9428+
}
9429+
94119430
include "AArch64InstrAtomics.td"
94129431
include "AArch64SVEInstrInfo.td"
94139432
include "AArch64SMEInstrInfo.td"

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4163,3 +4163,24 @@ let Predicates = [HasSVE2orSME2, HasLUT] in {
41634163
// LUTI4 (two contiguous registers)
41644164
defm LUTI4_Z2ZZI : sve2_luti4_vector_vg2_index<"luti4">;
41654165
} // End HasSVE2orSME2, HasLUT
4166+
4167+
//===----------------------------------------------------------------------===//
4168+
// Checked Pointer Arithmetic (FEAT_CPA)
4169+
//===----------------------------------------------------------------------===//
4170+
let Predicates = [HasSVEorSME, HasCPA] in {
4171+
// Add/subtract (vectors, unpredicated)
4172+
def ADD_ZZZ_CPA : sve_int_bin_cons_arit_0<0b11, 0b010, "addpt", ZPR64>;
4173+
def SUB_ZZZ_CPA : sve_int_bin_cons_arit_0<0b11, 0b011, "subpt", ZPR64>;
4174+
4175+
// Add/subtract (vectors, predicated)
4176+
let DestructiveInstType = DestructiveBinaryComm in {
4177+
def ADD_ZPmZ_CPA : sve_int_bin_pred_arit_log<0b11, 0b00, 0b100, "addpt", ZPR64>;
4178+
def SUB_ZPmZ_CPA : sve_int_bin_pred_arit_log<0b11, 0b00, 0b101, "subpt", ZPR64>;
4179+
}
4180+
4181+
// Multiply-add vectors, writing multiplicand
4182+
def MAD_CPA : sve_int_mad_cpa<"madpt">;
4183+
4184+
// Multiply-add vectors, writing addend
4185+
def MLA_CPA : sve_int_mla_cpa<"mlapt">;
4186+
}

‎llvm/lib/Target/AArch64/AArch64SchedA64FX.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ def A64FXModel : SchedMachineModel {
2424
[HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, HasSVE2BitPerm, HasPAuth,
2525
HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16, HasSME2, HasSME2p1, HasSVE2p1,
2626
HasSVE2p1_or_HasSME2p1, HasSMEF16F16, HasSSVE_FP8FMA, HasSMEF8F16, HasSMEF8F32,
27-
HasSMEFA64];
27+
HasSMEFA64, HasCPA];
2828

2929
let FullInstRWOverlapCheck = 0;
3030
}

‎llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ def NeoverseN2Model : SchedMachineModel {
1919
let CompleteModel = 1;
2020

2121
list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
22-
[HasSVE2p1]);
22+
[HasSVE2p1, HasCPA]);
2323
}
2424

2525
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ def NeoverseV1Model : SchedMachineModel {
2828

2929
list<Predicate> UnsupportedFeatures = !listconcat(SVE2Unsupported.F,
3030
SMEUnsupported.F,
31-
[HasMTE]);
31+
[HasMTE, HasCPA]);
3232
}
3333

3434
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ def NeoverseV2Model : SchedMachineModel {
2222
let CompleteModel = 1;
2323

2424
list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
25-
[HasSVE2p1]);
25+
[HasSVE2p1, HasCPA]);
2626
}
2727

2828
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1541,6 +1541,13 @@ class AArch64Operand : public MCParsedAsmOperand {
15411541
getShiftExtendAmount() <= 4;
15421542
}
15431543

1544+
bool isLSLImm3Shift() const {
1545+
if (!isShiftExtend())
1546+
return false;
1547+
AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1548+
return ET == AArch64_AM::LSL && getShiftExtendAmount() <= 7;
1549+
}
1550+
15441551
template<int Width> bool isMemXExtend() const {
15451552
if (!isExtend())
15461553
return false;
@@ -2091,6 +2098,12 @@ class AArch64Operand : public MCParsedAsmOperand {
20912098
Inst.addOperand(MCOperand::createImm(Imm));
20922099
}
20932100

2101+
void addLSLImm3ShifterOperands(MCInst &Inst, unsigned N) const {
2102+
assert(N == 1 && "Invalid number of operands!");
2103+
unsigned Imm = getShiftExtendAmount();
2104+
Inst.addOperand(MCOperand::createImm(Imm));
2105+
}
2106+
20942107
void addSyspXzrPairOperand(MCInst &Inst, unsigned N) const {
20952108
assert(N == 1 && "Invalid number of operands!");
20962109

@@ -3664,6 +3677,7 @@ static const struct Extension {
36643677
{"sme-f8f16", {AArch64::FeatureSMEF8F16}},
36653678
{"sme-f8f32", {AArch64::FeatureSMEF8F32}},
36663679
{"sme-fa64", {AArch64::FeatureSMEFA64}},
3680+
{"cpa", {AArch64::FeatureCPA}},
36673681
};
36683682

36693683
static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
@@ -6064,6 +6078,9 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
60646078
"Invalid vector list, expected list with each SVE vector in the list "
60656079
"4 registers apart, and the first register in the range [z0, z3] or "
60666080
"[z16, z19] and with correct element type");
6081+
case Match_AddSubLSLImm3ShiftLarge:
6082+
return Error(Loc,
6083+
"expected 'lsl' with optional integer in range [0, 7]");
60676084
default:
60686085
llvm_unreachable("unexpected error code!");
60696086
}
@@ -6448,6 +6465,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
64486465
case Match_InvalidMemoryIndexed8:
64496466
case Match_InvalidMemoryIndexed16:
64506467
case Match_InvalidCondCode:
6468+
case Match_AddSubLSLImm3ShiftLarge:
64516469
case Match_AddSubRegExtendSmall:
64526470
case Match_AddSubRegExtendLarge:
64536471
case Match_AddSubSecondSource:

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10424,3 +10424,34 @@ multiclass sve2_luti4_vector_vg2_index<string mnemonic> {
1042410424
let Inst{23-22} = idx;
1042510425
}
1042610426
}
10427+
10428+
//===----------------------------------------------------------------------===//
10429+
// Checked Pointer Arithmetic (FEAT_CPA)
10430+
//===----------------------------------------------------------------------===//
10431+
class sve_int_mad_cpa<string asm>
10432+
: I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, ZPR64:$Zm, ZPR64:$Za),
10433+
asm, "\t$Zdn, $Zm, $Za", "", []>, Sched<[]> {
10434+
bits<5> Zdn;
10435+
bits<5> Zm;
10436+
bits<5> Za;
10437+
let Inst{31-24} = 0b01000100;
10438+
let Inst{23-22} = 0b11; // sz
10439+
let Inst{21} = 0b0;
10440+
let Inst{20-16} = Zm;
10441+
let Inst{15} = 0b1;
10442+
let Inst{14-10} = 0b10110; // opc
10443+
let Inst{9-5} = Za;
10444+
let Inst{4-0} = Zdn;
10445+
10446+
let Constraints = "$Zdn = $_Zdn";
10447+
let DestructiveInstType = DestructiveOther;
10448+
let ElementSize = ZPR64.ElementSize;
10449+
let hasSideEffects = 0;
10450+
}
10451+
10452+
class sve_int_mla_cpa<string asm>
10453+
: sve2_int_mla<0b11, 0b10100, asm, ZPR64, ZPR64> {
10454+
let Inst{15} = 0b1;
10455+
10456+
let ElementSize = ZPR64.ElementSize;
10457+
}

‎llvm/test/MC/AArch64/SVE/armv9.5a-cpa.s

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,69 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve -mattr=+cpa < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme -mattr=+cpa < %s \
4+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+cpa < %s 2>&1 \
8+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR-NO-SVESME
9+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s 2>&1 \
10+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR-NO-CPA
11+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s 2>&1 \
12+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR-NO-CPA
13+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve -mattr=+cpa < %s \
14+
// RUN: | llvm-objdump -d --mattr=+sve --mattr=+cpa - \
15+
// RUN: | FileCheck %s --check-prefix=CHECK-INST
16+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve -mattr=+cpa < %s \
17+
// RUN: | llvm-objdump -d --mattr=+sve --mattr=-cpa - \
18+
// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
19+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve -mattr=+cpa < %s \
20+
// RUN: | llvm-objdump -d --mattr=-sve --mattr=+cpa - \
21+
// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
22+
23+
addpt z23.d, z13.d, z8.d
24+
// CHECK-INST: addpt z23.d, z13.d, z8.d
25+
// CHECK-ENCODING: [0xb7,0x09,0xe8,0x04]
26+
// CHECK-ERROR: instruction requires: cpa sve or sme
27+
// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
28+
// CHECK-ERROR-NO-CPA: instruction requires: cpa
29+
// CHECK-UNKNOWN: 04e809b7 <unknown>
30+
31+
addpt z23.d, p3/m, z23.d, z13.d
32+
// CHECK-INST: addpt z23.d, p3/m, z23.d, z13.d
33+
// CHECK-ENCODING: [0xb7,0x0d,0xc4,0x04]
34+
// CHECK-ERROR: instruction requires: cpa sve or sme
35+
// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
36+
// CHECK-ERROR-NO-CPA: instruction requires: cpa
37+
// CHECK-UNKNOWN: 04c40db7 <unknown>
38+
39+
subpt z23.d, z13.d, z8.d
40+
// CHECK-INST: subpt z23.d, z13.d, z8.d
41+
// CHECK-ENCODING: [0xb7,0x0d,0xe8,0x04]
42+
// CHECK-ERROR: instruction requires: cpa sve or sme
43+
// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
44+
// CHECK-ERROR-NO-CPA: instruction requires: cpa
45+
// CHECK-UNKNOWN: 04e80db7 <unknown>
46+
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subpt z23.d, p3/m, z23.d, z13.d
48+
// CHECK-INST: subpt z23.d, p3/m, z23.d, z13.d
49+
// CHECK-ENCODING: [0xb7,0x0d,0xc5,0x04]
50+
// CHECK-ERROR: instruction requires: cpa sve or sme
51+
// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
52+
// CHECK-ERROR-NO-CPA: instruction requires: cpa
53+
// CHECK-UNKNOWN: 04c50db7 <unknown>
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madpt z0.d, z1.d, z31.d
56+
// CHECK-INST: madpt z0.d, z1.d, z31.d
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// CHECK-ENCODING: [0xe0,0xdb,0xc1,0x44]
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// CHECK-ERROR: instruction requires: cpa sve or sme
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// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
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// CHECK-ERROR-NO-CPA: instruction requires: cpa
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// CHECK-UNKNOWN: 44c1dbe0 <unknown>
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mlapt z0.d, z1.d, z31.d
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// CHECK-INST: mlapt z0.d, z1.d, z31.d
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// CHECK-ENCODING: [0x20,0xd0,0xdf,0x44]
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// CHECK-ERROR: instruction requires: cpa sve or sme
67+
// CHECK-ERROR-NO-SVESME: instruction requires: sve or sme
68+
// CHECK-ERROR-NO-CPA: instruction requires: cpa
69+
// CHECK-UNKNOWN: 44dfd020 <unknown>

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