[AArch64] Use 64-bit movi for zeroing halfs/floats

This was using the .2d variant which zeros 128 bits, but using the .2s variant
that zeros 64 bits is faster on some cores.

This is a prep step for D99586 to always using movi for zeroing floats.

Differential Revision: https://reviews.llvm.org/D99710

Author: Sjoerd Meijer

llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp

@@ -1091,17 +1091,16 @@ void AArch64AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI) {
 void AArch64AsmPrinter::EmitFMov0(const MachineInstr &MI) {
   Register DestReg = MI.getOperand(0).getReg();
   if (STI->hasZeroCycleZeroingFP() && !STI->hasZeroCycleZeroingFPWorkaround()) {
-    // Convert H/S/D register to corresponding Q register
+    // Convert H/S register to corresponding D register
     if (AArch64::H0 <= DestReg && DestReg <= AArch64::H31)
-      DestReg = AArch64::Q0 + (DestReg - AArch64::H0);
+      DestReg = AArch64::D0 + (DestReg - AArch64::H0);
     else if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31)
-      DestReg = AArch64::Q0 + (DestReg - AArch64::S0);
-    else {
+      DestReg = AArch64::D0 + (DestReg - AArch64::S0);
+    else
       assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31);
-      DestReg = AArch64::Q0 + (DestReg - AArch64::D0);
-    }
+
     MCInst MOVI;
-    MOVI.setOpcode(AArch64::MOVIv2d_ns);
+    MOVI.setOpcode(AArch64::MOVID);
     MOVI.addOperand(MCOperand::createReg(DestReg));
     MOVI.addOperand(MCOperand::createImm(0));
     EmitToStreamer(*OutStreamer, MOVI);

llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll

@@ -28,13 +28,13 @@ entry:
 ; NONE16: fmov d2, xzr
 ; NONE16: movi{{(.16b)?}} v3{{(.2d)?}}, #0
 ; ZEROFP-DAG: ldr h0,{{.*}}
-; ZEROFP-DAG: movi v{{[0-3]+}}.2d, #0
-; ZEROFP-DAG: movi v{{[0-3]+}}.2d, #0
-; ZEROFP-DAG: movi v{{[0-3]+}}.2d, #0
-; ZERO16: movi v{{[0-3]+}}.2d, #0
-; ZERO16: movi v{{[0-3]+}}.2d, #0
-; ZERO16: movi v{{[0-3]+}}.2d, #0
-; ZERO16: movi v{{[0-3]+}}.2d, #0
+; ZEROFP-DAG: movi d1, #0
+; ZEROFP-DAG: movi d2, #0
+; ZEROFP-DAG: movi v3.2d, #0
+; ZERO16: movi d0, #0
+; ZERO16: movi d1, #0
+; ZERO16: movi d2, #0
+; ZERO16: movi v3.2d, #0
   tail call void @bar(half 0.000000e+00, float 0.000000e+00, double 0.000000e+00, <2 x double> <double 0.000000e+00, double 0.000000e+00>) nounwind
   ret void
 }
@@ -65,8 +65,8 @@ define void @t4() nounwind ssp {
 ; ALL-LABEL: t4:
 ; NONEFP: fmov s{{[0-3]+}}, wzr
 ; NONEFP: fmov s{{[0-3]+}}, wzr
-; ZEROFP: movi v{{[0-3]+}}.2d, #0
-; ZEROFP: movi v{{[0-3]+}}.2d, #0
+; ZEROFP: movi d0, #0
+; ZEROFP: movi d1, #0
   tail call void @barf(float 0.000000e+00, float 0.000000e+00) nounwind
   ret void
 }
@@ -147,15 +147,15 @@ define float @tf32() {
 entry:
 ; ALL-LABEL: tf32:
 ; NONEFP: mov s0, wzr
-; ZEROFP: movi v0.2d, #0
+; ZEROFP: movi d0, #0
   ret float 0.0
 }
 
 define double @td64() {
 entry:
 ; ALL-LABEL: td64:
 ; NONEFP: mov d0, xzr
-; ZEROFP: movi v0.2d, #0
+; ZEROFP: movi d0, #0
   ret double 0.0
 }
 

llvm/test/CodeGen/AArch64/f16-imm.ll

@@ -11,7 +11,7 @@ define half @Const0() {
 ;
 ; CHECK-ZCZ-LABEL: Const0:
 ; CHECK-ZCZ:       // %bb.0: // %entry
-; CHECK-ZCZ-NEXT:    movi v0.2d, #0000000000000000
+; CHECK-ZCZ-NEXT:    movi d0, #0
 ; CHECK-ZCZ-NEXT:    ret
 ;
 ; CHECK-NOFP16-LABEL: Const0: