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#include " llvm/Support/raw_ostream.h"
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#include " llvm/TableGen/Record.h"
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- namespace llvm {
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-
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static constexpr int WebAssemblyInstructionTableSize = 256 ;
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- void emitWebAssemblyDisassemblerTables (
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+ void llvm:: emitWebAssemblyDisassemblerTables (
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raw_ostream &OS,
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- const ArrayRef<const CodeGenInstruction *> & NumberedInstructions) {
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+ ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
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// First lets organize all opcodes by (prefix) byte. Prefix 0 is the
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// starting table.
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std::map<unsigned ,
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std::map<unsigned , std::pair<unsigned , const CodeGenInstruction *>>>
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OpcodeTable;
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for (unsigned I = 0 ; I != NumberedInstructions.size (); ++I) {
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- auto &CGI = *NumberedInstructions[I];
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- auto &Def = *CGI.TheDef ;
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+ const CodeGenInstruction &CGI = *NumberedInstructions[I];
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+ const Record &Def = *CGI.TheDef ;
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if (!Def.getValue (" Inst" ))
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continue ;
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- auto &Inst = *Def.getValueAsBitsInit (" Inst" );
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- RecordKeeper &RK = Inst.getRecordKeeper ();
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- unsigned Opc = static_cast <unsigned >(
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- cast<IntInit>(Inst.convertInitializerTo (IntRecTy::get (RK)))
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- ->getValue ());
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+ const BitsInit &Inst = *Def.getValueAsBitsInit (" Inst" );
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+ unsigned Opc = static_cast <unsigned >(*Inst.convertInitializerToInt ());
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if (Opc == 0xFFFFFFFF )
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continue ; // No opcode defined.
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assert (Opc <= 0xFFFFFF );
@@ -97,14 +92,14 @@ void emitWebAssemblyDisassemblerTables(
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OS << " };\n\n " ;
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std::vector<std::string> OperandTable, CurOperandList;
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// Output one table per prefix.
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- for (auto &PrefixPair : OpcodeTable) {
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- if (PrefixPair. second .empty ())
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+ for (const auto &[Prefix, Table] : OpcodeTable) {
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+ if (Table .empty ())
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continue ;
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- OS << " WebAssemblyInstruction InstructionTable" << PrefixPair. first ;
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+ OS << " WebAssemblyInstruction InstructionTable" << Prefix ;
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OS << " [] = {\n " ;
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for (unsigned I = 0 ; I < WebAssemblyInstructionTableSize; I++) {
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- auto InstIt = PrefixPair. second .find (I);
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- if (InstIt != PrefixPair. second .end ()) {
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+ auto InstIt = Table .find (I);
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+ if (InstIt != Table .end ()) {
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// Regular instruction.
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assert (InstIt->second .second );
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auto &CGI = *InstIt->second .second ;
@@ -144,7 +139,7 @@ void emitWebAssemblyDisassemblerTables(
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} else {
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auto PrefixIt = OpcodeTable.find (I);
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// If we have a non-empty table for it that's not 0, this is a prefix.
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- if (PrefixIt != OpcodeTable.end () && I && !PrefixPair. first ) {
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+ if (PrefixIt != OpcodeTable.end () && I && !Prefix ) {
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OS << " { 0, ET_Prefix, 0, 0" ;
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} else {
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OS << " { 0, ET_Unused, 0, 0" ;
@@ -163,15 +158,11 @@ void emitWebAssemblyDisassemblerTables(
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// Create a table of all extension tables:
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OS << " struct { uint8_t Prefix; const WebAssemblyInstruction *Table; }\n " ;
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OS << " PrefixTable[] = {\n " ;
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- for (auto &PrefixPair : OpcodeTable) {
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- if (PrefixPair. second . empty () || !PrefixPair. first )
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+ for (const auto &[Prefix, Table] : OpcodeTable) {
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+ if (Table. empty () || !Prefix )
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continue ;
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- OS << " { " << PrefixPair.first << " , InstructionTable"
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- << PrefixPair.first ;
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- OS << " },\n " ;
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+ OS << " { " << Prefix << " , InstructionTable" << Prefix << " },\n " ;
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}
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OS << " { 0, nullptr }\n };\n\n " ;
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OS << " } // end namespace llvm\n " ;
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}
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-
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- } // namespace llvm
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