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[RISCV][GISel] Restore s32 support on RV64 for DIV, and REM.
This reverts commit 2599d69. I was was plannig to remove s32 as a legal type on RV64, but I'm rethinking that.
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5 files changed

+293
-122
lines changed

5 files changed

+293
-122
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -450,9 +450,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
450450

451451
if (ST.hasStdExtM()) {
452452
getActionDefinitionsBuilder({G_UDIV, G_SDIV, G_UREM, G_SREM})
453-
.legalFor({sXLen})
453+
.legalFor({s32, sXLen})
454454
.libcallFor({sDoubleXLen})
455-
.clampScalar(0, sXLen, sDoubleXLen)
455+
.clampScalar(0, s32, sDoubleXLen)
456456
.widenScalarToNextPow2(0);
457457
} else {
458458
getActionDefinitionsBuilder({G_UDIV, G_SDIV, G_UREM, G_SREM})

‎llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll

Lines changed: 4 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -348,9 +348,7 @@ define i32 @sdiv_i32(i32 %a, i32 %b) {
348348
;
349349
; RV64IM-LABEL: sdiv_i32:
350350
; RV64IM: # %bb.0: # %entry
351-
; RV64IM-NEXT: sext.w a0, a0
352-
; RV64IM-NEXT: sext.w a1, a1
353-
; RV64IM-NEXT: div a0, a0, a1
351+
; RV64IM-NEXT: divw a0, a0, a1
354352
; RV64IM-NEXT: ret
355353
entry:
356354
%0 = sdiv i32 %a, %b
@@ -365,9 +363,7 @@ define i32 @srem_i32(i32 %a, i32 %b) {
365363
;
366364
; RV64IM-LABEL: srem_i32:
367365
; RV64IM: # %bb.0: # %entry
368-
; RV64IM-NEXT: sext.w a0, a0
369-
; RV64IM-NEXT: sext.w a1, a1
370-
; RV64IM-NEXT: rem a0, a0, a1
366+
; RV64IM-NEXT: remw a0, a0, a1
371367
; RV64IM-NEXT: ret
372368
entry:
373369
%0 = srem i32 %a, %b
@@ -382,11 +378,7 @@ define i32 @udiv_i32(i32 %a, i32 %b) {
382378
;
383379
; RV64IM-LABEL: udiv_i32:
384380
; RV64IM: # %bb.0: # %entry
385-
; RV64IM-NEXT: slli a0, a0, 32
386-
; RV64IM-NEXT: srli a0, a0, 32
387-
; RV64IM-NEXT: slli a1, a1, 32
388-
; RV64IM-NEXT: srli a1, a1, 32
389-
; RV64IM-NEXT: divu a0, a0, a1
381+
; RV64IM-NEXT: divuw a0, a0, a1
390382
; RV64IM-NEXT: ret
391383
entry:
392384
%0 = udiv i32 %a, %b
@@ -401,11 +393,7 @@ define i32 @urem_i32(i32 %a, i32 %b) {
401393
;
402394
; RV64IM-LABEL: urem_i32:
403395
; RV64IM: # %bb.0: # %entry
404-
; RV64IM-NEXT: slli a0, a0, 32
405-
; RV64IM-NEXT: srli a0, a0, 32
406-
; RV64IM-NEXT: slli a1, a1, 32
407-
; RV64IM-NEXT: srli a1, a1, 32
408-
; RV64IM-NEXT: remu a0, a0, a1
396+
; RV64IM-NEXT: remuw a0, a0, a1
409397
; RV64IM-NEXT: ret
410398
entry:
411399
%0 = urem i32 %a, %b

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir

Lines changed: 135 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,141 @@
22
# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
33
# RUN: | FileCheck -check-prefix=RV64I %s
44

5+
---
6+
name: mul_i32
7+
legalized: true
8+
regBankSelected: true
9+
tracksRegLiveness: true
10+
body: |
11+
bb.0.entry:
12+
liveins: $x10, $x11
13+
14+
; RV64I-LABEL: name: mul_i32
15+
; RV64I: liveins: $x10, $x11
16+
; RV64I-NEXT: {{ $}}
17+
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18+
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
19+
; RV64I-NEXT: [[MULW:%[0-9]+]]:gpr = MULW [[COPY]], [[COPY1]]
20+
; RV64I-NEXT: $x10 = COPY [[MULW]]
21+
; RV64I-NEXT: PseudoRET implicit $x10
22+
%0:gprb(s64) = COPY $x10
23+
%1:gprb(s32) = G_TRUNC %0(s64)
24+
%2:gprb(s64) = COPY $x11
25+
%3:gprb(s32) = G_TRUNC %2(s64)
26+
%4:gprb(s32) = G_MUL %1, %3
27+
%5:gprb(s64) = G_ANYEXT %4(s32)
28+
$x10 = COPY %5(s64)
29+
PseudoRET implicit $x10
30+
31+
...
32+
---
33+
name: sdiv_i32
34+
legalized: true
35+
regBankSelected: true
36+
tracksRegLiveness: true
37+
body: |
38+
bb.0.entry:
39+
liveins: $x10, $x11
40+
41+
; RV64I-LABEL: name: sdiv_i32
42+
; RV64I: liveins: $x10, $x11
43+
; RV64I-NEXT: {{ $}}
44+
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
45+
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
46+
; RV64I-NEXT: [[DIVW:%[0-9]+]]:gpr = DIVW [[COPY]], [[COPY1]]
47+
; RV64I-NEXT: $x10 = COPY [[DIVW]]
48+
; RV64I-NEXT: PseudoRET implicit $x10
49+
%0:gprb(s64) = COPY $x10
50+
%1:gprb(s32) = G_TRUNC %0(s64)
51+
%2:gprb(s64) = COPY $x11
52+
%3:gprb(s32) = G_TRUNC %2(s64)
53+
%4:gprb(s32) = G_SDIV %1, %3
54+
%5:gprb(s64) = G_ANYEXT %4(s32)
55+
$x10 = COPY %5(s64)
56+
PseudoRET implicit $x10
57+
58+
...
59+
---
60+
name: srem_i32
61+
legalized: true
62+
regBankSelected: true
63+
tracksRegLiveness: true
64+
body: |
65+
bb.0.entry:
66+
liveins: $x10, $x11
67+
68+
; RV64I-LABEL: name: srem_i32
69+
; RV64I: liveins: $x10, $x11
70+
; RV64I-NEXT: {{ $}}
71+
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
72+
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
73+
; RV64I-NEXT: [[REMW:%[0-9]+]]:gpr = REMW [[COPY]], [[COPY1]]
74+
; RV64I-NEXT: $x10 = COPY [[REMW]]
75+
; RV64I-NEXT: PseudoRET implicit $x10
76+
%0:gprb(s64) = COPY $x10
77+
%1:gprb(s32) = G_TRUNC %0(s64)
78+
%2:gprb(s64) = COPY $x11
79+
%3:gprb(s32) = G_TRUNC %2(s64)
80+
%4:gprb(s32) = G_SREM %1, %3
81+
%5:gprb(s64) = G_ANYEXT %4(s32)
82+
$x10 = COPY %5(s64)
83+
PseudoRET implicit $x10
84+
85+
...
86+
---
87+
name: udiv_i32
88+
legalized: true
89+
regBankSelected: true
90+
tracksRegLiveness: true
91+
body: |
92+
bb.0.entry:
93+
liveins: $x10, $x11
94+
95+
; RV64I-LABEL: name: udiv_i32
96+
; RV64I: liveins: $x10, $x11
97+
; RV64I-NEXT: {{ $}}
98+
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
99+
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
100+
; RV64I-NEXT: [[DIVUW:%[0-9]+]]:gpr = DIVUW [[COPY]], [[COPY1]]
101+
; RV64I-NEXT: $x10 = COPY [[DIVUW]]
102+
; RV64I-NEXT: PseudoRET implicit $x10
103+
%0:gprb(s64) = COPY $x10
104+
%1:gprb(s32) = G_TRUNC %0(s64)
105+
%2:gprb(s64) = COPY $x11
106+
%3:gprb(s32) = G_TRUNC %2(s64)
107+
%4:gprb(s32) = G_UDIV %1, %3
108+
%5:gprb(s64) = G_ANYEXT %4(s32)
109+
$x10 = COPY %5(s64)
110+
PseudoRET implicit $x10
111+
112+
...
113+
---
114+
name: urem_i32
115+
legalized: true
116+
regBankSelected: true
117+
tracksRegLiveness: true
118+
body: |
119+
bb.0.entry:
120+
liveins: $x10, $x11
121+
122+
; RV64I-LABEL: name: urem_i32
123+
; RV64I: liveins: $x10, $x11
124+
; RV64I-NEXT: {{ $}}
125+
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
126+
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
127+
; RV64I-NEXT: [[REMUW:%[0-9]+]]:gpr = REMUW [[COPY]], [[COPY1]]
128+
; RV64I-NEXT: $x10 = COPY [[REMUW]]
129+
; RV64I-NEXT: PseudoRET implicit $x10
130+
%0:gprb(s64) = COPY $x10
131+
%1:gprb(s32) = G_TRUNC %0(s64)
132+
%2:gprb(s64) = COPY $x11
133+
%3:gprb(s32) = G_TRUNC %2(s64)
134+
%4:gprb(s32) = G_UREM %1, %3
135+
%5:gprb(s64) = G_ANYEXT %4(s32)
136+
$x10 = COPY %5(s64)
137+
PseudoRET implicit $x10
138+
139+
...
5140
---
6141
name: mul_i64
7142
legalized: true

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir

Lines changed: 76 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -28,14 +28,19 @@ body: |
2828
; CHECK-M-LABEL: name: sdiv_i8
2929
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
3030
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
31-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
32-
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
33-
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
34-
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
35-
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
36-
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
37-
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[ASHR]], [[ASHR1]]
38-
; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s64)
31+
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
32+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
33+
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s64)
34+
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
35+
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
36+
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
37+
; CHECK-M-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
38+
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C2]](s64)
39+
; CHECK-M-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
40+
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C3]](s64)
41+
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
42+
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SDIV]](s32)
43+
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
3944
; CHECK-M-NEXT: PseudoRET implicit $x10
4045
%0:_(s64) = COPY $x10
4146
%1:_(s64) = COPY $x11
@@ -72,14 +77,19 @@ body: |
7277
; CHECK-M-LABEL: name: sdiv_i15
7378
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
7479
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
75-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 49
76-
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
77-
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
78-
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 49
79-
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
80-
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
81-
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[ASHR]], [[ASHR1]]
82-
; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s64)
80+
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
81+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
82+
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s64)
83+
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
84+
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
85+
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
86+
; CHECK-M-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
87+
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C2]](s64)
88+
; CHECK-M-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 17
89+
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C3]](s64)
90+
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
91+
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SDIV]](s32)
92+
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
8393
; CHECK-M-NEXT: PseudoRET implicit $x10
8494
%0:_(s64) = COPY $x10
8595
%1:_(s64) = COPY $x11
@@ -116,14 +126,19 @@ body: |
116126
; CHECK-M-LABEL: name: sdiv_i16
117127
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
118128
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
119-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
120-
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
121-
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
122-
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
123-
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C1]](s64)
124-
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL1]], [[C1]](s64)
125-
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[ASHR]], [[ASHR1]]
126-
; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s64)
129+
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
130+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
131+
; CHECK-M-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s64)
132+
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
133+
; CHECK-M-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s64)
134+
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
135+
; CHECK-M-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
136+
; CHECK-M-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C2]](s64)
137+
; CHECK-M-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
138+
; CHECK-M-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C3]](s64)
139+
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
140+
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SDIV]](s32)
141+
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
127142
; CHECK-M-NEXT: PseudoRET implicit $x10
128143
%0:_(s64) = COPY $x10
129144
%1:_(s64) = COPY $x11
@@ -156,10 +171,11 @@ body: |
156171
; CHECK-M-LABEL: name: sdiv_i32
157172
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
158173
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
159-
; CHECK-M-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
160-
; CHECK-M-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
161-
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
162-
; CHECK-M-NEXT: $x10 = COPY [[SDIV]](s64)
174+
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
175+
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
176+
; CHECK-M-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[TRUNC]], [[TRUNC1]]
177+
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SDIV]](s32)
178+
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
163179
; CHECK-M-NEXT: PseudoRET implicit $x10
164180
%0:_(s64) = COPY $x10
165181
%1:_(s64) = COPY $x11
@@ -342,12 +358,15 @@ body: |
342358
; CHECK-M-LABEL: name: udiv_i8
343359
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
344360
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
345-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
346-
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
347-
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
348-
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
349-
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[AND]], [[AND1]]
350-
; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s64)
361+
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
362+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
363+
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
364+
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
365+
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
366+
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
367+
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
368+
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UDIV]](s32)
369+
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
351370
; CHECK-M-NEXT: PseudoRET implicit $x10
352371
%0:_(s64) = COPY $x10
353372
%1:_(s64) = COPY $x11
@@ -382,12 +401,15 @@ body: |
382401
; CHECK-M-LABEL: name: udiv_i15
383402
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
384403
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
385-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767
386-
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
387-
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767
388-
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
389-
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[AND]], [[AND1]]
390-
; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s64)
404+
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
405+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
406+
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
407+
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
408+
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
409+
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
410+
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
411+
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UDIV]](s32)
412+
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
391413
; CHECK-M-NEXT: PseudoRET implicit $x10
392414
%0:_(s64) = COPY $x10
393415
%1:_(s64) = COPY $x11
@@ -422,12 +444,15 @@ body: |
422444
; CHECK-M-LABEL: name: udiv_i16
423445
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
424446
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
425-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
426-
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
427-
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
428-
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
429-
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[AND]], [[AND1]]
430-
; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s64)
447+
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
448+
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
449+
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
450+
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
451+
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
452+
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
453+
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
454+
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UDIV]](s32)
455+
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
431456
; CHECK-M-NEXT: PseudoRET implicit $x10
432457
%0:_(s64) = COPY $x10
433458
%1:_(s64) = COPY $x11
@@ -462,12 +487,11 @@ body: |
462487
; CHECK-M-LABEL: name: udiv_i32
463488
; CHECK-M: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
464489
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
465-
; CHECK-M-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
466-
; CHECK-M-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
467-
; CHECK-M-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
468-
; CHECK-M-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
469-
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[AND]], [[AND1]]
470-
; CHECK-M-NEXT: $x10 = COPY [[UDIV]](s64)
490+
; CHECK-M-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
491+
; CHECK-M-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
492+
; CHECK-M-NEXT: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[TRUNC]], [[TRUNC1]]
493+
; CHECK-M-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UDIV]](s32)
494+
; CHECK-M-NEXT: $x10 = COPY [[ANYEXT]](s64)
471495
; CHECK-M-NEXT: PseudoRET implicit $x10
472496
%0:_(s64) = COPY $x10
473497
%1:_(s64) = COPY $x11

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