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1 parent 2ba20c5 commit f024aabCopy full SHA for f024aab
llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
@@ -2,8 +2,6 @@
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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-; TODO: lbu and lhu should be selected to avoid the unnecessary masking.
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-
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@bytes = dso_local global [5 x i8] zeroinitializer, align 1
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define dso_local i32 @test_zext_i8() nounwind {
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