Skip to content

Commit f05db78

Browse files
committed
[SDAG] Address review comments. NFC.
1 parent f97a84c commit f05db78

File tree

5 files changed

+14
-14
lines changed

5 files changed

+14
-14
lines changed

llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1022,7 +1022,7 @@ END_TWO_BYTE_PACK()
10221022

10231023
SDNodeFlags getFlags() const { return Flags; }
10241024
void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; }
1025-
void clearFlags(unsigned Mask) { Flags &= ~Mask; }
1025+
void dropFlags(unsigned Mask) { Flags &= ~Mask; }
10261026

10271027
/// Clear any flags in this node that aren't also set in Flags.
10281028
/// If Flags is not in a defined state then this has no effect.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1210,7 +1210,7 @@ SDValue DAGCombiner::reassociateOpsCommutative(unsigned Opc, const SDLoc &DL,
12101210
SDNodeFlags NewFlags;
12111211
if (N0.getOpcode() == ISD::ADD && N0->getFlags().hasNoUnsignedWrap() &&
12121212
Flags.hasNoUnsignedWrap())
1213-
NewFlags = SDNodeFlags::NoUnsignedWrap;
1213+
NewFlags |= SDNodeFlags::NoUnsignedWrap;
12141214

12151215
if (DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
12161216
// Reassociate: (op (op x, c1), c2) -> (op x, (op c1, c2))
@@ -2892,7 +2892,7 @@ SDValue DAGCombiner::visitADDLike(SDNode *N) {
28922892
if (N->getFlags().hasNoUnsignedWrap() &&
28932893
N0->getFlags().hasNoUnsignedWrap() &&
28942894
N0.getOperand(0)->getFlags().hasNoUnsignedWrap()) {
2895-
Flags = SDNodeFlags::NoUnsignedWrap;
2895+
Flags |= SDNodeFlags::NoUnsignedWrap;
28962896
if (N->getFlags().hasNoSignedWrap() &&
28972897
N0->getFlags().hasNoSignedWrap() &&
28982898
N0.getOperand(0)->getFlags().hasNoSignedWrap())
@@ -2920,7 +2920,7 @@ SDValue DAGCombiner::visitADDLike(SDNode *N) {
29202920
N0->getFlags().hasNoUnsignedWrap() &&
29212921
OMul->getFlags().hasNoUnsignedWrap() &&
29222922
OMul.getOperand(0)->getFlags().hasNoUnsignedWrap()) {
2923-
Flags = SDNodeFlags::NoUnsignedWrap;
2923+
Flags |= SDNodeFlags::NoUnsignedWrap;
29242924
if (N->getFlags().hasNoSignedWrap() &&
29252925
N0->getFlags().hasNoSignedWrap() &&
29262926
OMul->getFlags().hasNoSignedWrap() &&
@@ -10195,7 +10195,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
1019510195
SDNodeFlags Flags;
1019610196
// Preserve the disjoint flag for Or.
1019710197
if (N0.getOpcode() == ISD::OR && N0->getFlags().hasDisjoint())
10198-
Flags = SDNodeFlags::Disjoint;
10198+
Flags |= SDNodeFlags::Disjoint;
1019910199
return DAG.getNode(N0.getOpcode(), DL, VT, Shl0, Shl1, Flags);
1020010200
}
1020110201
}

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4318,7 +4318,7 @@ void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
43184318
SDNodeFlags Flags;
43194319
if (NW.hasNoUnsignedWrap() ||
43204320
(int64_t(Offset) >= 0 && NW.hasNoUnsignedSignedWrap()))
4321-
Flags = SDNodeFlags::NoUnsignedWrap;
4321+
Flags |= SDNodeFlags::NoUnsignedWrap;
43224322

43234323
N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
43244324
DAG.getConstant(Offset, dl, N.getValueType()), Flags);

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1489,13 +1489,13 @@ bool TargetLowering::SimplifyDemandedBits(
14891489
SDNodeFlags Flags = Op.getNode()->getFlags();
14901490
if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO,
14911491
Depth + 1)) {
1492-
Op->clearFlags(SDNodeFlags::Disjoint);
1492+
Op->dropFlags(SDNodeFlags::Disjoint);
14931493
return true;
14941494
}
14951495

14961496
if (SimplifyDemandedBits(Op0, ~Known.One & DemandedBits, DemandedElts,
14971497
Known2, TLO, Depth + 1)) {
1498-
Op->clearFlags(SDNodeFlags::Disjoint);
1498+
Op->dropFlags(SDNodeFlags::Disjoint);
14991499
return true;
15001500
}
15011501

@@ -1802,7 +1802,7 @@ bool TargetLowering::SimplifyDemandedBits(
18021802
Depth + 1)) {
18031803
// Disable the nsw and nuw flags. We can no longer guarantee that we
18041804
// won't wrap after simplification.
1805-
Op->clearFlags(SDNodeFlags::NoWrap);
1805+
Op->dropFlags(SDNodeFlags::NoWrap);
18061806
return true;
18071807
}
18081808
Known.Zero <<= ShAmt;
@@ -1888,7 +1888,7 @@ bool TargetLowering::SimplifyDemandedBits(
18881888
Depth + 1)) {
18891889
// Disable the nsw and nuw flags. We can no longer guarantee that we
18901890
// won't wrap after simplification.
1891-
Op->clearFlags(SDNodeFlags::NoWrap);
1891+
Op->dropFlags(SDNodeFlags::NoWrap);
18921892
return true;
18931893
}
18941894
Known.resetAll();
@@ -2444,7 +2444,7 @@ bool TargetLowering::SimplifyDemandedBits(
24442444
APInt InDemandedElts = DemandedElts.zext(InElts);
24452445
if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
24462446
Depth + 1)) {
2447-
Op->clearFlags(SDNodeFlags::NonNeg);
2447+
Op->dropFlags(SDNodeFlags::NonNeg);
24482448
return true;
24492449
}
24502450
assert(Known.getBitWidth() == InBits && "Src width has changed?");
@@ -2508,7 +2508,7 @@ bool TargetLowering::SimplifyDemandedBits(
25082508
if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) {
25092509
SDNodeFlags Flags;
25102510
if (!IsVecInReg)
2511-
Flags = SDNodeFlags::NonNeg;
2511+
Flags |= SDNodeFlags::NonNeg;
25122512
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src, Flags));
25132513
}
25142514
}
@@ -2818,7 +2818,7 @@ bool TargetLowering::SimplifyDemandedBits(
28182818
ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) {
28192819
// Disable the nsw and nuw flags. We can no longer guarantee that we
28202820
// won't wrap after simplification.
2821-
Op->clearFlags(SDNodeFlags::NoWrap);
2821+
Op->dropFlags(SDNodeFlags::NoWrap);
28222822
return true;
28232823
}
28242824

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2676,7 +2676,7 @@ static void adjustForSubtraction(SelectionDAG &DAG, const SDLoc &DL,
26762676
(N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
26772677
// Disable the nsw and nuw flags: the backend needs to handle
26782678
// overflow as well during comparison elimination.
2679-
N->clearFlags(SDNodeFlags::NoWrap);
2679+
N->dropFlags(SDNodeFlags::NoWrap);
26802680
C.Op0 = SDValue(N, 0);
26812681
C.Op1 = DAG.getConstant(0, DL, N->getValueType(0));
26822682
return;

0 commit comments

Comments
 (0)