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Convert as many LivePhysRegs uses to LiveRegUnits
Additionally, remove unused #include "llvm/CodeGen/LivePhysRegs.h"
1 parent 662d821 commit f0d6c61

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8 files changed

+76
-80
lines changed

8 files changed

+76
-80
lines changed

‎llvm/lib/CodeGen/ReachingDefAnalysis.cpp

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -6,10 +6,10 @@
66
//
77
//===----------------------------------------------------------------------===//
88

9-
#include "llvm/ADT/SmallSet.h"
10-
#include "llvm/ADT/SetOperations.h"
11-
#include "llvm/CodeGen/LivePhysRegs.h"
129
#include "llvm/CodeGen/ReachingDefAnalysis.h"
10+
#include "llvm/ADT/SetOperations.h"
11+
#include "llvm/ADT/SmallSet.h"
12+
#include "llvm/CodeGen/LiveRegUnits.h"
1313
#include "llvm/CodeGen/TargetRegisterInfo.h"
1414
#include "llvm/CodeGen/TargetSubtargetInfo.h"
1515
#include "llvm/Support/Debug.h"
@@ -421,9 +421,9 @@ void ReachingDefAnalysis::getLiveOuts(MachineBasicBlock *MBB,
421421
return;
422422

423423
VisitedBBs.insert(MBB);
424-
LivePhysRegs LiveRegs(*TRI);
424+
LiveRegUnits LiveRegs(*TRI);
425425
LiveRegs.addLiveOuts(*MBB);
426-
if (LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
426+
if (LiveRegs.available(PhysReg))
427427
return;
428428

429429
if (auto *Def = getLocalLiveOutMIDef(MBB, PhysReg))
@@ -469,19 +469,19 @@ MachineInstr *ReachingDefAnalysis::getMIOperand(MachineInstr *MI,
469469
bool ReachingDefAnalysis::isRegUsedAfter(MachineInstr *MI,
470470
MCRegister PhysReg) const {
471471
MachineBasicBlock *MBB = MI->getParent();
472-
LivePhysRegs LiveRegs(*TRI);
472+
LiveRegUnits LiveRegs(*TRI);
473473
LiveRegs.addLiveOuts(*MBB);
474474

475475
// Yes if the register is live out of the basic block.
476-
if (!LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
476+
if (!LiveRegs.available(PhysReg))
477477
return true;
478478

479479
// Walk backwards through the block to see if the register is live at some
480480
// point.
481481
for (MachineInstr &Last :
482482
instructionsWithoutDebug(MBB->instr_rbegin(), MBB->instr_rend())) {
483483
LiveRegs.stepBackward(Last);
484-
if (!LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
484+
if (!LiveRegs.available(PhysReg))
485485
return InstIds.lookup(&Last) > InstIds.lookup(MI);
486486
}
487487
return false;
@@ -504,9 +504,9 @@ bool ReachingDefAnalysis::isRegDefinedAfter(MachineInstr *MI,
504504
bool ReachingDefAnalysis::isReachingDefLiveOut(MachineInstr *MI,
505505
MCRegister PhysReg) const {
506506
MachineBasicBlock *MBB = MI->getParent();
507-
LivePhysRegs LiveRegs(*TRI);
507+
LiveRegUnits LiveRegs(*TRI);
508508
LiveRegs.addLiveOuts(*MBB);
509-
if (LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
509+
if (LiveRegs.available(PhysReg))
510510
return false;
511511

512512
auto Last = MBB->getLastNonDebugInstr();
@@ -525,9 +525,9 @@ bool ReachingDefAnalysis::isReachingDefLiveOut(MachineInstr *MI,
525525
MachineInstr *
526526
ReachingDefAnalysis::getLocalLiveOutMIDef(MachineBasicBlock *MBB,
527527
MCRegister PhysReg) const {
528-
LivePhysRegs LiveRegs(*TRI);
528+
LiveRegUnits LiveRegs(*TRI);
529529
LiveRegs.addLiveOuts(*MBB);
530-
if (LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
530+
if (LiveRegs.available(PhysReg))
531531
return nullptr;
532532

533533
auto Last = MBB->getLastNonDebugInstr();

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -197,6 +197,7 @@
197197
#include "llvm/ADT/SmallVector.h"
198198
#include "llvm/ADT/Statistic.h"
199199
#include "llvm/CodeGen/LivePhysRegs.h"
200+
#include "llvm/CodeGen/LiveRegUnits.h"
200201
#include "llvm/CodeGen/MachineBasicBlock.h"
201202
#include "llvm/CodeGen/MachineFrameInfo.h"
202203
#include "llvm/CodeGen/MachineFunction.h"
@@ -988,7 +989,7 @@ void AArch64FrameLowering::emitZeroCallUsedRegs(BitVector RegsToZero,
988989
}
989990
}
990991

991-
static void getLiveRegsForEntryMBB(LivePhysRegs &LiveRegs,
992+
static void getLiveRegsForEntryMBB(LiveRegUnits &LiveRegs,
992993
const MachineBasicBlock &MBB) {
993994
const MachineFunction *MF = MBB.getParent();
994995
LiveRegs.addLiveIns(MBB);
@@ -1018,16 +1019,15 @@ static Register findScratchNonCalleeSaveRegister(MachineBasicBlock *MBB) {
10181019

10191020
const AArch64Subtarget &Subtarget = MF->getSubtarget<AArch64Subtarget>();
10201021
const AArch64RegisterInfo &TRI = *Subtarget.getRegisterInfo();
1021-
LivePhysRegs LiveRegs(TRI);
1022+
LiveRegUnits LiveRegs(TRI);
10221023
getLiveRegsForEntryMBB(LiveRegs, *MBB);
10231024

10241025
// Prefer X9 since it was historically used for the prologue scratch reg.
1025-
const MachineRegisterInfo &MRI = MF->getRegInfo();
1026-
if (LiveRegs.available(MRI, AArch64::X9))
1026+
if (LiveRegs.available(AArch64::X9))
10271027
return AArch64::X9;
10281028

1029-
for (unsigned Reg : AArch64::GPR64RegClass) {
1030-
if (LiveRegs.available(MRI, Reg))
1029+
for (Register Reg : AArch64::GPR64RegClass) {
1030+
if (LiveRegs.available(Reg))
10311031
return Reg;
10321032
}
10331033
return AArch64::NoRegister;
@@ -1044,13 +1044,11 @@ bool AArch64FrameLowering::canUseAsPrologue(
10441044

10451045
if (AFI->hasSwiftAsyncContext()) {
10461046
const AArch64RegisterInfo &TRI = *Subtarget.getRegisterInfo();
1047-
const MachineRegisterInfo &MRI = MF->getRegInfo();
1048-
LivePhysRegs LiveRegs(TRI);
1047+
LiveRegUnits LiveRegs(TRI);
10491048
getLiveRegsForEntryMBB(LiveRegs, MBB);
10501049
// The StoreSwiftAsyncContext clobbers X16 and X17. Make sure they are
10511050
// available.
1052-
if (!LiveRegs.available(MRI, AArch64::X16) ||
1053-
!LiveRegs.available(MRI, AArch64::X17))
1051+
if (!LiveRegs.available(AArch64::X16) || !LiveRegs.available(AArch64::X17))
10541052
return false;
10551053
}
10561054

‎llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
1212
#include "SIRegisterInfo.h"
1313
#include "llvm/ADT/SmallVector.h"
14-
#include "llvm/CodeGen/LivePhysRegs.h"
14+
#include "llvm/CodeGen/LiveRegUnits.h"
1515
#include "llvm/CodeGen/MachineFunctionPass.h"
1616
#include "llvm/CodeGen/MachineOperand.h"
1717
#include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -313,7 +313,7 @@ MachineBasicBlock::reverse_iterator SIOptimizeExecMasking::findExecCopy(
313313
return E;
314314
}
315315

316-
// XXX - Seems LivePhysRegs doesn't work correctly since it will incorrectly
316+
// XXX - Seems LiveRegUnits doesn't work correctly since it will incorrectly
317317
// report the register as unavailable because a super-register with a lane mask
318318
// is unavailable.
319319
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg) {
@@ -383,7 +383,7 @@ bool SIOptimizeExecMasking::isRegisterInUseBetween(MachineInstr &Stop,
383383
MCRegister Reg,
384384
bool UseLiveOuts,
385385
bool IgnoreStart) const {
386-
LivePhysRegs LR(*TRI);
386+
LiveRegUnits LR(*TRI);
387387
if (UseLiveOuts)
388388
LR.addLiveOuts(*Stop.getParent());
389389

@@ -396,7 +396,7 @@ bool SIOptimizeExecMasking::isRegisterInUseBetween(MachineInstr &Stop,
396396
LR.stepBackward(*A);
397397
}
398398

399-
return !LR.available(*MRI, Reg);
399+
return !LR.available(Reg);
400400
}
401401

402402
// Determine if a register Reg is not re-defined and still in use

‎llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@
3131
#include "llvm/ADT/Statistic.h"
3232
#include "llvm/ADT/iterator_range.h"
3333
#include "llvm/Analysis/AliasAnalysis.h"
34-
#include "llvm/CodeGen/LivePhysRegs.h"
34+
#include "llvm/CodeGen/LiveRegUnits.h"
3535
#include "llvm/CodeGen/MachineBasicBlock.h"
3636
#include "llvm/CodeGen/MachineDominators.h"
3737
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -109,7 +109,7 @@ namespace {
109109
const ARMSubtarget *STI;
110110
const TargetLowering *TL;
111111
ARMFunctionInfo *AFI;
112-
LivePhysRegs LiveRegs;
112+
LiveRegUnits LiveRegs;
113113
RegisterClassInfo RegClassInfo;
114114
MachineBasicBlock::const_iterator LiveRegPos;
115115
bool LiveRegsValid;
@@ -589,7 +589,7 @@ unsigned ARMLoadStoreOpt::findFreeReg(const TargetRegisterClass &RegClass) {
589589
}
590590

591591
for (unsigned Reg : RegClassInfo.getOrder(&RegClass))
592-
if (LiveRegs.available(MF->getRegInfo(), Reg))
592+
if (LiveRegs.available(Reg))
593593
return Reg;
594594
return 0;
595595
}

‎llvm/lib/Target/ARM/Thumb1FrameLowering.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -601,11 +601,11 @@ bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
601601

602602
static void findTemporariesForLR(const BitVector &GPRsNoLRSP,
603603
const BitVector &PopFriendly,
604-
const LivePhysRegs &UsedRegs, unsigned &PopReg,
604+
const LiveRegUnits &UsedRegs, unsigned &PopReg,
605605
unsigned &TmpReg, MachineRegisterInfo &MRI) {
606606
PopReg = TmpReg = 0;
607607
for (auto Reg : GPRsNoLRSP.set_bits()) {
608-
if (UsedRegs.available(MRI, Reg)) {
608+
if (UsedRegs.available(Reg)) {
609609
// Remember the first pop-friendly register and exit.
610610
if (PopFriendly.test(Reg)) {
611611
PopReg = Reg;
@@ -673,7 +673,7 @@ bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
673673
// Look for a temporary register to use.
674674
// First, compute the liveness information.
675675
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
676-
LivePhysRegs UsedRegs(TRI);
676+
LiveRegUnits UsedRegs(TRI);
677677
UsedRegs.addLiveOuts(MBB);
678678
// The semantic of pristines changed recently and now,
679679
// the callee-saved registers that are touched in the function

‎llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1036,15 +1036,27 @@ false:
10361036
define void @stack_realign2(i32 %a, i32 %b, ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr %ptr4, ptr %ptr5, ptr %ptr6) {
10371037
; ENABLE-LABEL: stack_realign2:
10381038
; ENABLE: ; %bb.0:
1039+
; ENABLE-NEXT: lsl w8, w1, w0
1040+
; ENABLE-NEXT: lsr w9, w0, w1
1041+
; ENABLE-NEXT: lsl w14, w0, w1
1042+
; ENABLE-NEXT: lsr w11, w1, w0
1043+
; ENABLE-NEXT: add w15, w1, w0
1044+
; ENABLE-NEXT: sub w10, w8, w9
1045+
; ENABLE-NEXT: subs w17, w1, w0
1046+
; ENABLE-NEXT: add w16, w14, w8
1047+
; ENABLE-NEXT: add w12, w9, w11
1048+
; ENABLE-NEXT: add w13, w11, w15
1049+
; ENABLE-NEXT: b.le LBB14_2
1050+
; ENABLE-NEXT: ; %bb.1: ; %true
10391051
; ENABLE-NEXT: stp x28, x27, [sp, #-96]! ; 16-byte Folded Spill
10401052
; ENABLE-NEXT: stp x26, x25, [sp, #16] ; 16-byte Folded Spill
10411053
; ENABLE-NEXT: stp x24, x23, [sp, #32] ; 16-byte Folded Spill
10421054
; ENABLE-NEXT: stp x22, x21, [sp, #48] ; 16-byte Folded Spill
10431055
; ENABLE-NEXT: stp x20, x19, [sp, #64] ; 16-byte Folded Spill
10441056
; ENABLE-NEXT: stp x29, x30, [sp, #80] ; 16-byte Folded Spill
10451057
; ENABLE-NEXT: add x29, sp, #80
1046-
; ENABLE-NEXT: sub x9, sp, #32
1047-
; ENABLE-NEXT: and sp, x9, #0xffffffffffffffe0
1058+
; ENABLE-NEXT: sub x18, sp, #32
1059+
; ENABLE-NEXT: and sp, x18, #0xffffffffffffffe0
10481060
; ENABLE-NEXT: .cfi_def_cfa w29, 16
10491061
; ENABLE-NEXT: .cfi_offset w30, -8
10501062
; ENABLE-NEXT: .cfi_offset w29, -16
@@ -1058,22 +1070,17 @@ define void @stack_realign2(i32 %a, i32 %b, ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr
10581070
; ENABLE-NEXT: .cfi_offset w26, -80
10591071
; ENABLE-NEXT: .cfi_offset w27, -88
10601072
; ENABLE-NEXT: .cfi_offset w28, -96
1061-
; ENABLE-NEXT: lsl w8, w1, w0
1062-
; ENABLE-NEXT: lsr w9, w0, w1
1063-
; ENABLE-NEXT: lsl w14, w0, w1
1064-
; ENABLE-NEXT: lsr w11, w1, w0
1065-
; ENABLE-NEXT: add w15, w1, w0
1066-
; ENABLE-NEXT: sub w10, w8, w9
1067-
; ENABLE-NEXT: subs w17, w1, w0
1068-
; ENABLE-NEXT: add w16, w14, w8
1069-
; ENABLE-NEXT: add w12, w9, w11
1070-
; ENABLE-NEXT: add w13, w11, w15
1071-
; ENABLE-NEXT: b.le LBB14_2
1072-
; ENABLE-NEXT: ; %bb.1: ; %true
10731073
; ENABLE-NEXT: str w0, [sp]
10741074
; ENABLE-NEXT: ; InlineAsm Start
10751075
; ENABLE-NEXT: nop
10761076
; ENABLE-NEXT: ; InlineAsm End
1077+
; ENABLE-NEXT: sub sp, x29, #80
1078+
; ENABLE-NEXT: ldp x29, x30, [sp, #80] ; 16-byte Folded Reload
1079+
; ENABLE-NEXT: ldp x20, x19, [sp, #64] ; 16-byte Folded Reload
1080+
; ENABLE-NEXT: ldp x22, x21, [sp, #48] ; 16-byte Folded Reload
1081+
; ENABLE-NEXT: ldp x24, x23, [sp, #32] ; 16-byte Folded Reload
1082+
; ENABLE-NEXT: ldp x26, x25, [sp, #16] ; 16-byte Folded Reload
1083+
; ENABLE-NEXT: ldp x28, x27, [sp], #96 ; 16-byte Folded Reload
10771084
; ENABLE-NEXT: LBB14_2: ; %false
10781085
; ENABLE-NEXT: str w14, [x2]
10791086
; ENABLE-NEXT: str w8, [x3]
@@ -1084,13 +1091,6 @@ define void @stack_realign2(i32 %a, i32 %b, ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr
10841091
; ENABLE-NEXT: stp w0, w1, [x2, #4]
10851092
; ENABLE-NEXT: stp w16, w10, [x2, #12]
10861093
; ENABLE-NEXT: stp w12, w13, [x2, #20]
1087-
; ENABLE-NEXT: sub sp, x29, #80
1088-
; ENABLE-NEXT: ldp x29, x30, [sp, #80] ; 16-byte Folded Reload
1089-
; ENABLE-NEXT: ldp x20, x19, [sp, #64] ; 16-byte Folded Reload
1090-
; ENABLE-NEXT: ldp x22, x21, [sp, #48] ; 16-byte Folded Reload
1091-
; ENABLE-NEXT: ldp x24, x23, [sp, #32] ; 16-byte Folded Reload
1092-
; ENABLE-NEXT: ldp x26, x25, [sp, #16] ; 16-byte Folded Reload
1093-
; ENABLE-NEXT: ldp x28, x27, [sp], #96 ; 16-byte Folded Reload
10941094
; ENABLE-NEXT: ret
10951095
;
10961096
; DISABLE-LABEL: stack_realign2:

‎llvm/test/CodeGen/AArch64/stack-probing-no-scratch-reg.mir

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -43,43 +43,43 @@ machineFunctionInfo: {}
4343
body: |
4444
; CHECK-LABEL: name: f
4545
; CHECK: bb.0.entry:
46-
; CHECK-NEXT: successors: %bb.3(0x80000000)
46+
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
4747
; CHECK-NEXT: liveins: $w0, $lr
4848
; CHECK-NEXT: {{ $}}
49+
; CHECK-NEXT: $x9 = IMPLICIT_DEF
50+
; CHECK-NEXT: dead $wzr = SUBSWri killed renamable $w0, 1, 0, implicit-def $nzcv
51+
; CHECK-NEXT: Bcc 12, %bb.2, implicit $nzcv
52+
; CHECK-NEXT: B %bb.1
53+
; CHECK-NEXT: {{ $}}
54+
; CHECK-NEXT: bb.1.if.then1:
55+
; CHECK-NEXT: successors: %bb.3(0x80000000)
56+
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x23, $x25, $x25, $x27, $x28, $lr
57+
; CHECK-NEXT: {{ $}}
4958
; CHECK-NEXT: early-clobber $sp = frame-setup STPXpre killed $fp, killed $lr, $sp, -2 :: (store (s64) into %stack.2), (store (s64) into %stack.1)
50-
; CHECK-NEXT: $x9 = frame-setup SUBXri $sp, 36, 12
59+
; CHECK-NEXT: $xzr = frame-setup SUBXri $sp, 36, 12
5160
; CHECK-NEXT: {{ $}}
52-
; CHECK-NEXT: bb.3.entry:
61+
; CHECK-NEXT: bb.3.if.then1:
5362
; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)
54-
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x25, $x27, $x28
5563
; CHECK-NEXT: {{ $}}
5664
; CHECK-NEXT: $sp = frame-setup SUBXri $sp, 1, 12
5765
; CHECK-NEXT: frame-setup STRXui $xzr, $sp, 0
58-
; CHECK-NEXT: $xzr = frame-setup SUBSXrx64 $sp, $x9, 24, implicit-def $nzcv
66+
; CHECK-NEXT: $xzr = frame-setup SUBSXrx64 $sp, $xzr, 24, implicit-def $nzcv
5967
; CHECK-NEXT: frame-setup Bcc 1, %bb.3, implicit $nzcv
6068
; CHECK-NEXT: {{ $}}
61-
; CHECK-NEXT: bb.4.entry:
62-
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
63-
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x25, $x27, $x28
69+
; CHECK-NEXT: bb.4.if.then1:
70+
; CHECK-NEXT: successors: %bb.2(0x80000000)
6471
; CHECK-NEXT: {{ $}}
6572
; CHECK-NEXT: $sp = frame-setup SUBXri $sp, 2544, 0
6673
; CHECK-NEXT: frame-setup STRXui $xzr, $sp, 0
67-
; CHECK-NEXT: $x9 = IMPLICIT_DEF
68-
; CHECK-NEXT: dead $wzr = SUBSWri killed renamable $w0, 1, 0, implicit-def $nzcv
69-
; CHECK-NEXT: Bcc 12, %bb.2, implicit $nzcv
70-
; CHECK-NEXT: B %bb.1
71-
; CHECK-NEXT: {{ $}}
72-
; CHECK-NEXT: bb.1.if.then1:
73-
; CHECK-NEXT: successors: %bb.2(0x80000000)
74-
; CHECK-NEXT: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x23, $x25, $x25, $x27, $x28
75-
; CHECK-NEXT: {{ $}}
7674
; CHECK-NEXT: $x0 = ADDXri $sp, 0, 0
7775
; CHECK-NEXT: BL @g, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
78-
; CHECK-NEXT: {{ $}}
79-
; CHECK-NEXT: bb.2.exit:
8076
; CHECK-NEXT: $sp = frame-destroy ADDXri $sp, 36, 12
8177
; CHECK-NEXT: $sp = frame-destroy ADDXri $sp, 2544, 0
8278
; CHECK-NEXT: early-clobber $sp, $fp, $lr = frame-destroy LDPXpost $sp, 2 :: (load (s64) from %stack.2), (load (s64) from %stack.1)
79+
; CHECK-NEXT: {{ $}}
80+
; CHECK-NEXT: bb.2.exit:
81+
; CHECK-NEXT: liveins: $lr
82+
; CHECK-NEXT: {{ $}}
8383
; CHECK-NEXT: RET_ReallyLR
8484
bb.0.entry:
8585
successors: %bb.1(0x40000000), %bb.2(0x40000000)

‎llvm/test/CodeGen/Thumb/PR35481.ll

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -18,11 +18,10 @@ define <4 x i32> @f() local_unnamed_addr #0 {
1818
; CHECK-V4T-NEXT: movs r2, #3
1919
; CHECK-V4T-NEXT: movs r3, #4
2020
; CHECK-V4T-NEXT: bl g
21+
; CHECK-V4T-NEXT: ldr r7, [sp, #4]
22+
; CHECK-V4T-NEXT: mov lr, r7
2123
; CHECK-V4T-NEXT: pop {r7}
22-
; CHECK-V4T-NEXT: mov r12, r0
23-
; CHECK-V4T-NEXT: pop {r0}
24-
; CHECK-V4T-NEXT: mov lr, r0
25-
; CHECK-V4T-NEXT: mov r0, r12
24+
; CHECK-V4T-NEXT: add sp, #4
2625
; CHECK-V4T-NEXT: bx lr
2726
;
2827
; CHECK-V8M-LABEL: f:
@@ -36,11 +35,10 @@ define <4 x i32> @f() local_unnamed_addr #0 {
3635
; CHECK-V8M-NEXT: movs r1, #2
3736
; CHECK-V8M-NEXT: movs r2, #3
3837
; CHECK-V8M-NEXT: movs r3, #4
38+
; CHECK-V8M-NEXT: ldr r7, [sp, #4]
39+
; CHECK-V8M-NEXT: mov lr, r7
3940
; CHECK-V8M-NEXT: pop {r7}
40-
; CHECK-V8M-NEXT: mov r12, r0
41-
; CHECK-V8M-NEXT: pop {r0}
42-
; CHECK-V8M-NEXT: mov lr, r0
43-
; CHECK-V8M-NEXT: mov r0, r12
41+
; CHECK-V8M-NEXT: add sp, #4
4442
; CHECK-V8M-NEXT: b g
4543
entry:
4644
%call = tail call i32 @h(i32 1)

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