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RKSimonRKSimon
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[DAG] visitEXTRACT_VECTOR_ELT - constant fold legal fp imm values (#74304)
If we're extracting a constant floating point value, and the constant is a legal fp imm value, then replace the extraction with a fp constant.
1 parent 155a013 commit f1200ca

11 files changed

+136
-576
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22243,6 +22243,19 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
2224322243
unsigned NumElts = VecVT.getVectorNumElements();
2224422244
unsigned VecEltBitWidth = VecVT.getScalarSizeInBits();
2224522245

22246+
// See if the extracted element is constant, in which case fold it if its
22247+
// a legal fp immediate.
22248+
if (IndexC && ScalarVT.isFloatingPoint()) {
22249+
APInt EltMask = APInt::getOneBitSet(NumElts, IndexC->getZExtValue());
22250+
KnownBits KnownElt = DAG.computeKnownBits(VecOp, EltMask);
22251+
if (KnownElt.isConstant()) {
22252+
APFloat CstFP =
22253+
APFloat(DAG.EVTToAPFloatSemantics(ScalarVT), KnownElt.getConstant());
22254+
if (TLI.isFPImmLegal(CstFP, ScalarVT))
22255+
return DAG.getConstantFP(CstFP, DL, ScalarVT);
22256+
}
22257+
}
22258+
2224622259
// TODO: These transforms should not require the 'hasOneUse' restriction, but
2224722260
// there are regressions on multiple targets without it. We can end up with a
2224822261
// mess of scalar and vector code if we reduce only part of the DAG to scalar.

‎llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -69,11 +69,10 @@ define void @insert_vec_v23i32_uaddlv_from_v8i16(ptr %0) {
6969
; CHECK: ; %bb.0: ; %entry
7070
; CHECK-NEXT: movi.2d v0, #0000000000000000
7171
; CHECK-NEXT: movi.2d v2, #0000000000000000
72-
; CHECK-NEXT: add x8, x0, #88
72+
; CHECK-NEXT: str wzr, [x0, #88]
7373
; CHECK-NEXT: uaddlv.8h s1, v0
7474
; CHECK-NEXT: stp q0, q0, [x0, #16]
7575
; CHECK-NEXT: stp q0, q0, [x0, #48]
76-
; CHECK-NEXT: st1.s { v0 }[2], [x8]
7776
; CHECK-NEXT: str d0, [x0, #80]
7877
; CHECK-NEXT: mov.s v2[0], v1[0]
7978
; CHECK-NEXT: ucvtf.4s v1, v2

‎llvm/test/CodeGen/AArch64/arm64-promote-const-complex-initializers.ll

Lines changed: 5 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -30,10 +30,10 @@ define [1 x <4 x float>] @test1() {
3030
define [1 x <4 x float>] @test2() {
3131
; CHECK-LABEL: .p2align 4, 0x0 ; -- Begin function test2
3232
; CHECK-NEXT: lCPI1_0:
33-
; CHECK-NEXT: .long 0x00000000 ; float 0
34-
; CHECK-NEXT: .long 0x00000000 ; float 0
35-
; CHECK-NEXT: .long 0x00000000 ; float 0
36-
; CHECK-NEXT: .long 0x3f800000 ; float 1
33+
; CHECK-NEXT: .long 0x80000000 ; float -0
34+
; CHECK-NEXT: .long 0x80000000 ; float -0
35+
; CHECK-NEXT: .long 0x80000000 ; float -0
36+
; CHECK-NEXT: .long 0xbf800000 ; float -1
3737
; CHECK-NEXT: .section __TEXT,__text,regular,pure_instructions
3838
; CHECK-NEXT: .globl _test2
3939
; CHECK-NEXT: .p2align 2
@@ -43,17 +43,7 @@ define [1 x <4 x float>] @test2() {
4343
; CHECK-NEXT: Lloh2:
4444
; CHECK-NEXT: adrp x8, lCPI1_0@PAGE
4545
; CHECK-NEXT: Lloh3:
46-
; CHECK-NEXT: ldr q1, [x8, lCPI1_0@PAGEOFF]
47-
; CHECK-NEXT: mov s2, v1[1]
48-
; CHECK-NEXT: fneg s0, s1
49-
; CHECK-NEXT: mov s3, v1[2]
50-
; CHECK-NEXT: mov s1, v1[3]
51-
; CHECK-NEXT: fneg s2, s2
52-
; CHECK-NEXT: fneg s3, s3
53-
; CHECK-NEXT: fneg s1, s1
54-
; CHECK-NEXT: mov.s v0[1], v2[0]
55-
; CHECK-NEXT: mov.s v0[2], v3[0]
56-
; CHECK-NEXT: mov.s v0[3], v1[0]
46+
; CHECK-NEXT: ldr q0, [x8, lCPI1_0@PAGEOFF]
5747
; CHECK-NEXT: ret
5848
;
5949
%constexpr = fneg float extractelement (<4 x float> bitcast (<1 x i128> <i128 84405977732342157929391748327801880576> to <4 x float>), i32 0)

‎llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -50,13 +50,12 @@ define void @zero_test() {
5050
; X86-LABEL: zero_test:
5151
; X86: # %bb.0: # %entry
5252
; X86-NEXT: xorps %xmm0, %xmm0
53-
; X86-NEXT: movlps %xmm0, (%eax)
53+
; X86-NEXT: movsd %xmm0, (%eax)
5454
; X86-NEXT: retl
5555
;
5656
; X64-LABEL: zero_test:
5757
; X64: # %bb.0: # %entry
58-
; X64-NEXT: xorps %xmm0, %xmm0
59-
; X64-NEXT: movlps %xmm0, (%rax)
58+
; X64-NEXT: movq $0, (%rax)
6059
; X64-NEXT: retq
6160
entry:
6261
%0 = select <2 x i1> undef, <2 x float> undef, <2 x float> zeroinitializer

‎llvm/test/CodeGen/X86/2012-07-10-extload64.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ define void @store_64(ptr %ptr) {
3030
; X86: # %bb.0: # %BB
3131
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
3232
; X86-NEXT: xorps %xmm0, %xmm0
33-
; X86-NEXT: movlps %xmm0, (%eax)
33+
; X86-NEXT: movsd %xmm0, (%eax)
3434
; X86-NEXT: retl
3535
;
3636
; X64-LABEL: store_64:

‎llvm/test/CodeGen/X86/fold-load-vec.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,8 +10,8 @@ define void @sample_test(ptr %source, ptr %dest) nounwind {
1010
; CHECK-NEXT: subq $24, %rsp
1111
; CHECK-NEXT: movq %rdi, {{[0-9]+}}(%rsp)
1212
; CHECK-NEXT: movq %rsi, {{[0-9]+}}(%rsp)
13+
; CHECK-NEXT: movq $0, (%rsp)
1314
; CHECK-NEXT: xorps %xmm0, %xmm0
14-
; CHECK-NEXT: movlps %xmm0, (%rsp)
1515
; CHECK-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
1616
; CHECK-NEXT: movlps %xmm0, (%rsp)
1717
; CHECK-NEXT: movlps %xmm0, (%rsi)

‎llvm/test/CodeGen/X86/half.ll

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1082,12 +1082,11 @@ define void @main.158() #0 {
10821082
; BWON-F16C-LABEL: main.158:
10831083
; BWON-F16C: # %bb.0: # %entry
10841084
; BWON-F16C-NEXT: vxorps %xmm0, %xmm0, %xmm0
1085-
; BWON-F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0
1086-
; BWON-F16C-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
1087-
; BWON-F16C-NEXT: vcvtph2ps %xmm0, %xmm0
1088-
; BWON-F16C-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
1089-
; BWON-F16C-NEXT: vucomiss %xmm0, %xmm1
1090-
; BWON-F16C-NEXT: vxorps %xmm0, %xmm0, %xmm0
1085+
; BWON-F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm1
1086+
; BWON-F16C-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
1087+
; BWON-F16C-NEXT: vcvtph2ps %xmm1, %xmm1
1088+
; BWON-F16C-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
1089+
; BWON-F16C-NEXT: vucomiss %xmm1, %xmm2
10911090
; BWON-F16C-NEXT: jae .LBB20_2
10921091
; BWON-F16C-NEXT: # %bb.1: # %entry
10931092
; BWON-F16C-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@@ -1100,8 +1099,7 @@ define void @main.158() #0 {
11001099
; CHECK-I686-LABEL: main.158:
11011100
; CHECK-I686: # %bb.0: # %entry
11021101
; CHECK-I686-NEXT: subl $12, %esp
1103-
; CHECK-I686-NEXT: pxor %xmm0, %xmm0
1104-
; CHECK-I686-NEXT: movd %xmm0, (%esp)
1102+
; CHECK-I686-NEXT: movl $0, (%esp)
11051103
; CHECK-I686-NEXT: calll __truncsfhf2
11061104
; CHECK-I686-NEXT: pextrw $0, %xmm0, %eax
11071105
; CHECK-I686-NEXT: movw %ax, (%esp)

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