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[LV][NFC] precommit test for EVL transform
A precommit test case to show vector loops generated from EVL transform - This is a precommit test for #92092
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‎llvm/test/Transforms/LoopVectorize/RISCV/evl-compatible-loops.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -passes=loop-vectorize -force-tail-folding-style=data-with-evl \
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; RUN: -prefer-predicate-over-epilogue=predicate-dont-vectorize \
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; RUN: -mtriple=riscv64 -mattr=+v -S < %s | FileCheck %s
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; Check loops having VPWidenIntOrFpInductionRecipe
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define void @foo(ptr noalias %a, i64 %N) {
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; CHECK-LABEL: define void @foo(
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; CHECK-SAME: ptr noalias [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = sub i64 -1, [[N]]
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; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 2
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]]
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; CHECK-NEXT: br i1 [[TMP3]], label [[SCALAR_PH:%.*]], label [[ENTRY:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 2
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; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP6]], 2
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; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[TMP7]], 1
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; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[N]], [[TMP8]]
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP5]]
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
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; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 2
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; CHECK-NEXT: [[TMP11:%.*]] = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
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; CHECK-NEXT: [[TMP12:%.*]] = add <vscale x 2 x i64> [[TMP11]], zeroinitializer
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; CHECK-NEXT: [[TMP13:%.*]] = mul <vscale x 2 x i64> [[TMP12]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
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; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 2 x i64> zeroinitializer, [[TMP13]]
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; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP15:%.*]] = mul i64 [[TMP14]], 2
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; CHECK-NEXT: [[TMP16:%.*]] = mul i64 1, [[TMP15]]
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; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP16]], i64 0
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; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDEX_EVL_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 2 x i64> [ [[INDUCTION]], [[ENTRY]] ], [ [[VEC_IND_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[TMP17:%.*]] = sub i64 [[N]], [[EVL_BASED_IV]]
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; CHECK-NEXT: [[TMP18:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[TMP17]], i32 2, i1 true)
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; CHECK-NEXT: [[TMP19:%.*]] = add i64 [[EVL_BASED_IV]], 0
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; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP19]]
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; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i64, ptr [[TMP20]], i32 0
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; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[VEC_IND]], ptr align 8 [[TMP21]], <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> poison, i1 true, i64 0), <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer), i32 [[TMP18]])
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; CHECK-NEXT: [[TMP22:%.*]] = zext i32 [[TMP18]] to i64
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; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP22]], [[EVL_BASED_IV]]
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], [[TMP10]]
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 2 x i64> [[VEC_IND]], [[DOTSPLAT]]
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; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i64 [[IV_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP23]], label [[MIDDLE_BLOCK:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: br i1 true, label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY1:%.*]] ]
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; CHECK-NEXT: br label [[FOR_BODY1:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT1:%.*]], [[FOR_BODY1]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV1]]
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; CHECK-NEXT: store i64 [[IV1]], ptr [[ARRAYIDX]], align 8
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; CHECK-NEXT: [[IV_NEXT1]] = add nuw nsw i64 [[IV1]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT1]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY1]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: for.cond.cleanup:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
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%arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv
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store i64 %iv, ptr %arrayidx, align 8
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %N
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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for.cond.cleanup:
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ret void
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}
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; Check loops having VPWidenPointerInductionRecipe
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define void @foo2(ptr noalias %a, ptr noalias %b, i64 %N) {
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; CHECK-LABEL: define void @foo2(
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; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = sub i64 -1, [[N]]
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; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 2
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]]
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; CHECK-NEXT: br i1 [[TMP3]], label [[SCALAR_PH:%.*]], label [[ENTRY:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 2
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; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP6]], 2
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; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[TMP7]], 1
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; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[N]], [[TMP8]]
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP5]]
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
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; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[N_VEC]], 8
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; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP9]]
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; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP11:%.*]] = mul i64 [[TMP10]], 2
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[B]], [[ENTRY]] ], [ [[PTR_IND:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDEX_EVL_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP13:%.*]] = mul i64 [[TMP12]], 2
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; CHECK-NEXT: [[TMP14:%.*]] = mul i64 [[TMP13]], 1
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; CHECK-NEXT: [[TMP15:%.*]] = mul i64 8, [[TMP14]]
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; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP13]], 0
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; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP16]], i64 0
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; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
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; CHECK-NEXT: [[TMP18:%.*]] = add <vscale x 2 x i64> [[DOTSPLAT]], [[TMP17]]
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; CHECK-NEXT: [[VECTOR_GEP:%.*]] = mul <vscale x 2 x i64> [[TMP18]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 8, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
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; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[POINTER_PHI]], <vscale x 2 x i64> [[VECTOR_GEP]]
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; CHECK-NEXT: [[TMP20:%.*]] = sub i64 [[N]], [[EVL_BASED_IV]]
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; CHECK-NEXT: [[TMP21:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[TMP20]], i32 2, i1 true)
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; CHECK-NEXT: [[TMP22:%.*]] = add i64 [[EVL_BASED_IV]], 0
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; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP22]]
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; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds ptr, ptr [[TMP23]], i32 0
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; CHECK-NEXT: call void @llvm.vp.store.nxv2p0.p0(<vscale x 2 x ptr> [[TMP19]], ptr align 8 [[TMP24]], <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> poison, i1 true, i64 0), <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer), i32 [[TMP21]])
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; CHECK-NEXT: [[TMP25:%.*]] = zext i32 [[TMP21]] to i64
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; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP25]], [[EVL_BASED_IV]]
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], [[TMP11]]
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; CHECK-NEXT: [[PTR_IND]] = getelementptr i8, ptr [[POINTER_PHI]], i64 [[TMP15]]
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; CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[IV_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP26]], label [[MIDDLE_BLOCK:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: br i1 true, label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY1:%.*]] ]
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; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[B]], [[ENTRY1]] ]
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; CHECK-NEXT: br label [[FOR_BODY1:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT1:%.*]], [[FOR_BODY1]] ]
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; CHECK-NEXT: [[ADDR:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], [[FOR_BODY1]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ]
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; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, ptr [[ADDR]], i64 8
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV1]]
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; CHECK-NEXT: store ptr [[ADDR]], ptr [[ARRAYIDX]], align 8
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; CHECK-NEXT: [[IV_NEXT1]] = add nuw nsw i64 [[IV1]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT1]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY1]], !llvm.loop [[LOOP5:![0-9]+]]
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; CHECK: for.cond.cleanup:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
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%addr = phi ptr [ %incdec.ptr, %for.body ], [ %b, %entry ]
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%incdec.ptr = getelementptr inbounds i8, ptr %addr, i64 8
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%arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv
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store ptr %addr, ptr %arrayidx, align 8
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %N
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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for.cond.cleanup:
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ret void
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}
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; Check loops having VPVectorPointerRecipe that access in reverse order
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define void @foo3(ptr noalias %a, i64 %N) {
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; CHECK-LABEL: define void @foo3(
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; CHECK-SAME: ptr noalias [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = sub i64 -1, [[N]]
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; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 2
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]]
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; CHECK-NEXT: br i1 [[TMP3]], label [[SCALAR_PH:%.*]], label [[ENTRY:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 2
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; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP6]], 2
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; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[TMP7]], 1
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; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[N]], [[TMP8]]
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP5]]
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
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; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[N_VEC]], -4
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; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP9]]
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; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP11:%.*]] = mul i64 [[TMP10]], 2
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[N]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[A]], [[ENTRY]] ], [ [[PTR_IND:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INDEX_EVL_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP13:%.*]] = mul i64 [[TMP12]], 2
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; CHECK-NEXT: [[TMP14:%.*]] = mul i64 [[TMP13]], 1
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; CHECK-NEXT: [[TMP15:%.*]] = mul i64 -4, [[TMP14]]
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; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP13]], 0
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; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP16]], i64 0
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; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
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; CHECK-NEXT: [[TMP18:%.*]] = add <vscale x 2 x i64> [[DOTSPLAT]], [[TMP17]]
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; CHECK-NEXT: [[VECTOR_GEP:%.*]] = mul <vscale x 2 x i64> [[TMP18]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -4, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
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; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[POINTER_PHI]], <vscale x 2 x i64> [[VECTOR_GEP]]
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; CHECK-NEXT: [[TMP20:%.*]] = sub i64 [[N]], [[EVL_BASED_IV]]
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; CHECK-NEXT: [[TMP21:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[TMP20]], i32 2, i1 true)
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; CHECK-NEXT: call void @llvm.vp.scatter.nxv2i64.nxv2p0(<vscale x 2 x i64> [[BROADCAST_SPLAT]], <vscale x 2 x ptr> align 8 [[TMP19]], <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> poison, i1 true, i64 0), <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer), i32 [[TMP21]])
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; CHECK-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64
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; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP22]], [[EVL_BASED_IV]]
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], [[TMP11]]
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; CHECK-NEXT: [[PTR_IND]] = getelementptr i8, ptr [[POINTER_PHI]], i64 [[TMP15]]
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; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i64 [[IV_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP23]], label [[MIDDLE_BLOCK:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: br i1 true, label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY1:%.*]] ]
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; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[A]], [[ENTRY1]] ]
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; CHECK-NEXT: br label [[FOR_BODY1:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT1:%.*]], [[FOR_BODY1]] ]
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; CHECK-NEXT: [[ADDR:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], [[FOR_BODY1]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ]
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; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, ptr [[ADDR]], i64 -4
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; CHECK-NEXT: store i64 [[N]], ptr [[ADDR]], align 8
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; CHECK-NEXT: [[IV_NEXT1]] = add nuw nsw i64 [[IV1]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT1]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY1]], !llvm.loop [[LOOP7:![0-9]+]]
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; CHECK: for.cond.cleanup:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
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%addr = phi ptr [ %incdec.ptr, %for.body ], [ %a, %entry ]
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%incdec.ptr = getelementptr inbounds i8, ptr %addr, i64 -4
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store i64 %N, ptr %addr, align 8
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %N
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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for.cond.cleanup:
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ret void
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}
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
255+
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
256+
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
257+
; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
258+
; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
259+
; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}
260+
;.

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