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[SDAG] neg x with only low bit demanded is x
We have a version of this transform in InstCombine, but surprisingly not in SDAG. Even more surprisingly, this benefits RISCV, but no other target. This was surprising enough I double checked my build configuration to make sure all targets were enabled; they appear to be. Differential Revision: https://reviews.llvm.org/D140324
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5 files changed

+29
-48
lines changed

5 files changed

+29
-48
lines changed

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2614,6 +2614,11 @@ bool TargetLowering::SimplifyDemandedBits(
26142614
return true;
26152615
}
26162616

2617+
// neg x with only low bit demanded is simply x.
2618+
if (Op.getOpcode() == ISD::SUB && DemandedBits.isOne() &&
2619+
isa<ConstantSDNode>(Op0) && cast<ConstantSDNode>(Op0)->isZero())
2620+
return TLO.CombineTo(Op, Op1);
2621+
26172622
// Attempt to avoid multi-use ops if we don't need anything from them.
26182623
if (!LoMask.isAllOnes() || !DemandedElts.isAllOnes()) {
26192624
SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(

‎llvm/test/CodeGen/RISCV/alu64.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -59,8 +59,7 @@ define i64 @sltiu(i64 %a) nounwind {
5959
; RV32I-LABEL: sltiu:
6060
; RV32I: # %bb.0:
6161
; RV32I-NEXT: sltiu a0, a0, 3
62-
; RV32I-NEXT: snez a1, a1
63-
; RV32I-NEXT: addi a1, a1, -1
62+
; RV32I-NEXT: seqz a1, a1
6463
; RV32I-NEXT: and a0, a1, a0
6564
; RV32I-NEXT: li a1, 0
6665
; RV32I-NEXT: ret

‎llvm/test/CodeGen/RISCV/bittest.ll

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -301,9 +301,7 @@ define i1 @bittest_constant_by_var_shr_i64(i64 %b) nounwind {
301301
; RV32-NEXT: srl a1, a1, a0
302302
; RV32-NEXT: addi a0, a0, -32
303303
; RV32-NEXT: slti a0, a0, 0
304-
; RV32-NEXT: neg a0, a0
305304
; RV32-NEXT: and a0, a0, a1
306-
; RV32-NEXT: andi a0, a0, 1
307305
; RV32-NEXT: ret
308306
;
309307
; RV64I-LABEL: bittest_constant_by_var_shr_i64:
@@ -335,9 +333,7 @@ define i1 @bittest_constant_by_var_shl_i64(i64 %b) nounwind {
335333
; RV32-NEXT: srl a1, a1, a0
336334
; RV32-NEXT: addi a0, a0, -32
337335
; RV32-NEXT: slti a0, a0, 0
338-
; RV32-NEXT: neg a0, a0
339336
; RV32-NEXT: and a0, a0, a1
340-
; RV32-NEXT: andi a0, a0, 1
341337
; RV32-NEXT: ret
342338
;
343339
; RV64I-LABEL: bittest_constant_by_var_shl_i64:

‎llvm/test/CodeGen/RISCV/forced-atomics.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2806,8 +2806,7 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind {
28062806
; RV32-NEXT: .LBB52_2: # %atomicrmw.start
28072807
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
28082808
; RV32-NEXT: sltiu a0, a4, 2
2809-
; RV32-NEXT: snez a2, a1
2810-
; RV32-NEXT: addi a2, a2, -1
2809+
; RV32-NEXT: seqz a2, a1
28112810
; RV32-NEXT: and a0, a2, a0
28122811
; RV32-NEXT: mv a2, a4
28132812
; RV32-NEXT: bnez a0, .LBB52_1

‎llvm/test/CodeGen/RISCV/fpclamptosat.ll

Lines changed: 22 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -115,8 +115,7 @@ define i32 @utest_f64i32(double %x) {
115115
; RV32IF-NEXT: .cfi_offset ra, -4
116116
; RV32IF-NEXT: call __fixunsdfdi@plt
117117
; RV32IF-NEXT: sltiu a2, a0, -1
118-
; RV32IF-NEXT: snez a1, a1
119-
; RV32IF-NEXT: addi a1, a1, -1
118+
; RV32IF-NEXT: seqz a1, a1
120119
; RV32IF-NEXT: and a1, a1, a2
121120
; RV32IF-NEXT: addi a1, a1, -1
122121
; RV32IF-NEXT: or a0, a1, a0
@@ -434,8 +433,7 @@ define i32 @utesth_f16i32(half %x) {
434433
; RV32-NEXT: call __extendhfsf2@plt
435434
; RV32-NEXT: call __fixunssfdi@plt
436435
; RV32-NEXT: sltiu a2, a0, -1
437-
; RV32-NEXT: snez a1, a1
438-
; RV32-NEXT: addi a1, a1, -1
436+
; RV32-NEXT: seqz a1, a1
439437
; RV32-NEXT: and a1, a1, a2
440438
; RV32-NEXT: addi a1, a1, -1
441439
; RV32-NEXT: or a0, a1, a0
@@ -1241,10 +1239,8 @@ define i64 @utest_f64i64(double %x) {
12411239
; RV32IF-NEXT: lw a1, 20(sp)
12421240
; RV32IF-NEXT: lw a2, 12(sp)
12431241
; RV32IF-NEXT: lw a3, 8(sp)
1244-
; RV32IF-NEXT: seqz a4, a0
1245-
; RV32IF-NEXT: snez a5, a1
1246-
; RV32IF-NEXT: addi a5, a5, -1
1247-
; RV32IF-NEXT: and a4, a5, a4
1242+
; RV32IF-NEXT: or a4, a1, a0
1243+
; RV32IF-NEXT: seqz a4, a4
12481244
; RV32IF-NEXT: xori a0, a0, 1
12491245
; RV32IF-NEXT: or a0, a0, a1
12501246
; RV32IF-NEXT: seqz a0, a0
@@ -1283,10 +1279,8 @@ define i64 @utest_f64i64(double %x) {
12831279
; RV32IFD-NEXT: lw a1, 20(sp)
12841280
; RV32IFD-NEXT: lw a2, 12(sp)
12851281
; RV32IFD-NEXT: lw a3, 8(sp)
1286-
; RV32IFD-NEXT: seqz a4, a0
1287-
; RV32IFD-NEXT: snez a5, a1
1288-
; RV32IFD-NEXT: addi a5, a5, -1
1289-
; RV32IFD-NEXT: and a4, a5, a4
1282+
; RV32IFD-NEXT: or a4, a1, a0
1283+
; RV32IFD-NEXT: seqz a4, a4
12901284
; RV32IFD-NEXT: xori a0, a0, 1
12911285
; RV32IFD-NEXT: or a0, a0, a1
12921286
; RV32IFD-NEXT: seqz a0, a0
@@ -1555,10 +1549,8 @@ define i64 @utest_f32i64(float %x) {
15551549
; RV32-NEXT: lw a1, 20(sp)
15561550
; RV32-NEXT: lw a2, 12(sp)
15571551
; RV32-NEXT: lw a3, 8(sp)
1558-
; RV32-NEXT: seqz a4, a0
1559-
; RV32-NEXT: snez a5, a1
1560-
; RV32-NEXT: addi a5, a5, -1
1561-
; RV32-NEXT: and a4, a5, a4
1552+
; RV32-NEXT: or a4, a1, a0
1553+
; RV32-NEXT: seqz a4, a4
15621554
; RV32-NEXT: xori a0, a0, 1
15631555
; RV32-NEXT: or a0, a0, a1
15641556
; RV32-NEXT: seqz a0, a0
@@ -1816,10 +1808,8 @@ define i64 @utesth_f16i64(half %x) {
18161808
; RV32-NEXT: lw a1, 20(sp)
18171809
; RV32-NEXT: lw a2, 12(sp)
18181810
; RV32-NEXT: lw a3, 8(sp)
1819-
; RV32-NEXT: seqz a4, a0
1820-
; RV32-NEXT: snez a5, a1
1821-
; RV32-NEXT: addi a5, a5, -1
1822-
; RV32-NEXT: and a4, a5, a4
1811+
; RV32-NEXT: or a4, a1, a0
1812+
; RV32-NEXT: seqz a4, a4
18231813
; RV32-NEXT: xori a0, a0, 1
18241814
; RV32-NEXT: or a0, a0, a1
18251815
; RV32-NEXT: seqz a0, a0
@@ -3234,11 +3224,9 @@ define i64 @utest_f64i64_mm(double %x) {
32343224
; RV32IF-NEXT: lw a1, 20(sp)
32353225
; RV32IF-NEXT: lw a2, 12(sp)
32363226
; RV32IF-NEXT: lw a3, 8(sp)
3237-
; RV32IF-NEXT: seqz a4, a0
3238-
; RV32IF-NEXT: snez a5, a1
3239-
; RV32IF-NEXT: addi a5, a5, -1
3240-
; RV32IF-NEXT: and a4, a5, a4
3241-
; RV32IF-NEXT: neg a4, a4
3227+
; RV32IF-NEXT: or a4, a1, a0
3228+
; RV32IF-NEXT: snez a4, a4
3229+
; RV32IF-NEXT: addi a4, a4, -1
32423230
; RV32IF-NEXT: and a3, a4, a3
32433231
; RV32IF-NEXT: xori a0, a0, 1
32443232
; RV32IF-NEXT: or a0, a0, a1
@@ -3281,11 +3269,9 @@ define i64 @utest_f64i64_mm(double %x) {
32813269
; RV32IFD-NEXT: lw a1, 20(sp)
32823270
; RV32IFD-NEXT: lw a2, 12(sp)
32833271
; RV32IFD-NEXT: lw a3, 8(sp)
3284-
; RV32IFD-NEXT: seqz a4, a0
3285-
; RV32IFD-NEXT: snez a5, a1
3286-
; RV32IFD-NEXT: addi a5, a5, -1
3287-
; RV32IFD-NEXT: and a4, a5, a4
3288-
; RV32IFD-NEXT: neg a4, a4
3272+
; RV32IFD-NEXT: or a4, a1, a0
3273+
; RV32IFD-NEXT: snez a4, a4
3274+
; RV32IFD-NEXT: addi a4, a4, -1
32893275
; RV32IFD-NEXT: and a3, a4, a3
32903276
; RV32IFD-NEXT: xori a0, a0, 1
32913277
; RV32IFD-NEXT: or a0, a0, a1
@@ -3601,11 +3587,9 @@ define i64 @utest_f32i64_mm(float %x) {
36013587
; RV32-NEXT: lw a1, 20(sp)
36023588
; RV32-NEXT: lw a2, 12(sp)
36033589
; RV32-NEXT: lw a3, 8(sp)
3604-
; RV32-NEXT: seqz a4, a0
3605-
; RV32-NEXT: snez a5, a1
3606-
; RV32-NEXT: addi a5, a5, -1
3607-
; RV32-NEXT: and a4, a5, a4
3608-
; RV32-NEXT: neg a4, a4
3590+
; RV32-NEXT: or a4, a1, a0
3591+
; RV32-NEXT: snez a4, a4
3592+
; RV32-NEXT: addi a4, a4, -1
36093593
; RV32-NEXT: and a3, a4, a3
36103594
; RV32-NEXT: xori a0, a0, 1
36113595
; RV32-NEXT: or a0, a0, a1
@@ -3914,11 +3898,9 @@ define i64 @utesth_f16i64_mm(half %x) {
39143898
; RV32-NEXT: lw a1, 20(sp)
39153899
; RV32-NEXT: lw a2, 12(sp)
39163900
; RV32-NEXT: lw a3, 8(sp)
3917-
; RV32-NEXT: seqz a4, a0
3918-
; RV32-NEXT: snez a5, a1
3919-
; RV32-NEXT: addi a5, a5, -1
3920-
; RV32-NEXT: and a4, a5, a4
3921-
; RV32-NEXT: neg a4, a4
3901+
; RV32-NEXT: or a4, a1, a0
3902+
; RV32-NEXT: snez a4, a4
3903+
; RV32-NEXT: addi a4, a4, -1
39223904
; RV32-NEXT: and a3, a4, a3
39233905
; RV32-NEXT: xori a0, a0, 1
39243906
; RV32-NEXT: or a0, a0, a1

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