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[AArch64][NFC] Pre-commit tests for Shift Left Long
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‎llvm/test/CodeGen/AArch64/neon-shift-left-long.ll

Lines changed: 186 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -1,201 +1,335 @@
1-
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
24

35
define <8 x i16> @test_sshll_v8i8(<8 x i8> %a) {
4-
; CHECK: test_sshll_v8i8:
5-
; CHECK: sshll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #3
6+
; CHECK-SD-LABEL: test_sshll_v8i8:
7+
; CHECK-SD: // %bb.0:
8+
; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #3
9+
; CHECK-SD-NEXT: ret
10+
;
11+
; CHECK-GI-LABEL: test_sshll_v8i8:
12+
; CHECK-GI: // %bb.0:
13+
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
14+
; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
15+
; CHECK-GI-NEXT: ret
616
%1 = sext <8 x i8> %a to <8 x i16>
717
%tmp = shl <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
818
ret <8 x i16> %tmp
919
}
1020

1121
define <4 x i32> @test_sshll_v4i16(<4 x i16> %a) {
12-
; CHECK: test_sshll_v4i16:
13-
; CHECK: sshll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #9
22+
; CHECK-SD-LABEL: test_sshll_v4i16:
23+
; CHECK-SD: // %bb.0:
24+
; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #9
25+
; CHECK-SD-NEXT: ret
26+
;
27+
; CHECK-GI-LABEL: test_sshll_v4i16:
28+
; CHECK-GI: // %bb.0:
29+
; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #0
30+
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
31+
; CHECK-GI-NEXT: ret
1432
%1 = sext <4 x i16> %a to <4 x i32>
1533
%tmp = shl <4 x i32> %1, <i32 9, i32 9, i32 9, i32 9>
1634
ret <4 x i32> %tmp
1735
}
1836

1937
define <2 x i64> @test_sshll_v2i32(<2 x i32> %a) {
20-
; CHECK: test_sshll_v2i32:
21-
; CHECK: sshll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #19
38+
; CHECK-SD-LABEL: test_sshll_v2i32:
39+
; CHECK-SD: // %bb.0:
40+
; CHECK-SD-NEXT: sshll v0.2d, v0.2s, #19
41+
; CHECK-SD-NEXT: ret
42+
;
43+
; CHECK-GI-LABEL: test_sshll_v2i32:
44+
; CHECK-GI: // %bb.0:
45+
; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #0
46+
; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
47+
; CHECK-GI-NEXT: ret
2248
%1 = sext <2 x i32> %a to <2 x i64>
2349
%tmp = shl <2 x i64> %1, <i64 19, i64 19>
2450
ret <2 x i64> %tmp
2551
}
2652

2753
define <8 x i16> @test_ushll_v8i8(<8 x i8> %a) {
28-
; CHECK: test_ushll_v8i8:
29-
; CHECK: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #3
54+
; CHECK-SD-LABEL: test_ushll_v8i8:
55+
; CHECK-SD: // %bb.0:
56+
; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #3
57+
; CHECK-SD-NEXT: ret
58+
;
59+
; CHECK-GI-LABEL: test_ushll_v8i8:
60+
; CHECK-GI: // %bb.0:
61+
; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
62+
; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
63+
; CHECK-GI-NEXT: ret
3064
%1 = zext <8 x i8> %a to <8 x i16>
3165
%tmp = shl <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
3266
ret <8 x i16> %tmp
3367
}
3468

3569
define <4 x i32> @test_ushll_v4i16(<4 x i16> %a) {
36-
; CHECK: test_ushll_v4i16:
37-
; CHECK: ushll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #9
70+
; CHECK-SD-LABEL: test_ushll_v4i16:
71+
; CHECK-SD: // %bb.0:
72+
; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #9
73+
; CHECK-SD-NEXT: ret
74+
;
75+
; CHECK-GI-LABEL: test_ushll_v4i16:
76+
; CHECK-GI: // %bb.0:
77+
; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
78+
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
79+
; CHECK-GI-NEXT: ret
3880
%1 = zext <4 x i16> %a to <4 x i32>
3981
%tmp = shl <4 x i32> %1, <i32 9, i32 9, i32 9, i32 9>
4082
ret <4 x i32> %tmp
4183
}
4284

4385
define <2 x i64> @test_ushll_v2i32(<2 x i32> %a) {
44-
; CHECK: test_ushll_v2i32:
45-
; CHECK: ushll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #19
86+
; CHECK-SD-LABEL: test_ushll_v2i32:
87+
; CHECK-SD: // %bb.0:
88+
; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #19
89+
; CHECK-SD-NEXT: ret
90+
;
91+
; CHECK-GI-LABEL: test_ushll_v2i32:
92+
; CHECK-GI: // %bb.0:
93+
; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0
94+
; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
95+
; CHECK-GI-NEXT: ret
4696
%1 = zext <2 x i32> %a to <2 x i64>
4797
%tmp = shl <2 x i64> %1, <i64 19, i64 19>
4898
ret <2 x i64> %tmp
4999
}
50100

51101
define <8 x i16> @test_sshll2_v16i8(<16 x i8> %a) {
52-
; CHECK: test_sshll2_v16i8:
53-
; CHECK: sshll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #3
102+
; CHECK-SD-LABEL: test_sshll2_v16i8:
103+
; CHECK-SD: // %bb.0:
104+
; CHECK-SD-NEXT: sshll2 v0.8h, v0.16b, #3
105+
; CHECK-SD-NEXT: ret
106+
;
107+
; CHECK-GI-LABEL: test_sshll2_v16i8:
108+
; CHECK-GI: // %bb.0:
109+
; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0
110+
; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
111+
; CHECK-GI-NEXT: ret
54112
%1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
55113
%2 = sext <8 x i8> %1 to <8 x i16>
56114
%tmp = shl <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
57115
ret <8 x i16> %tmp
58116
}
59117

60118
define <4 x i32> @test_sshll2_v8i16(<8 x i16> %a) {
61-
; CHECK: test_sshll2_v8i16:
62-
; CHECK: sshll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #9
119+
; CHECK-SD-LABEL: test_sshll2_v8i16:
120+
; CHECK-SD: // %bb.0:
121+
; CHECK-SD-NEXT: sshll2 v0.4s, v0.8h, #9
122+
; CHECK-SD-NEXT: ret
123+
;
124+
; CHECK-GI-LABEL: test_sshll2_v8i16:
125+
; CHECK-GI: // %bb.0:
126+
; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0
127+
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
128+
; CHECK-GI-NEXT: ret
63129
%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
64130
%2 = sext <4 x i16> %1 to <4 x i32>
65131
%tmp = shl <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9>
66132
ret <4 x i32> %tmp
67133
}
68134

69135
define <2 x i64> @test_sshll2_v4i32(<4 x i32> %a) {
70-
; CHECK: test_sshll2_v4i32:
71-
; CHECK: sshll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #19
136+
; CHECK-SD-LABEL: test_sshll2_v4i32:
137+
; CHECK-SD: // %bb.0:
138+
; CHECK-SD-NEXT: sshll2 v0.2d, v0.4s, #19
139+
; CHECK-SD-NEXT: ret
140+
;
141+
; CHECK-GI-LABEL: test_sshll2_v4i32:
142+
; CHECK-GI: // %bb.0:
143+
; CHECK-GI-NEXT: sshll2 v0.2d, v0.4s, #0
144+
; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
145+
; CHECK-GI-NEXT: ret
72146
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
73147
%2 = sext <2 x i32> %1 to <2 x i64>
74148
%tmp = shl <2 x i64> %2, <i64 19, i64 19>
75149
ret <2 x i64> %tmp
76150
}
77151

78152
define <8 x i16> @test_ushll2_v16i8(<16 x i8> %a) {
79-
; CHECK: test_ushll2_v16i8:
80-
; CHECK: ushll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #3
153+
; CHECK-SD-LABEL: test_ushll2_v16i8:
154+
; CHECK-SD: // %bb.0:
155+
; CHECK-SD-NEXT: ushll2 v0.8h, v0.16b, #3
156+
; CHECK-SD-NEXT: ret
157+
;
158+
; CHECK-GI-LABEL: test_ushll2_v16i8:
159+
; CHECK-GI: // %bb.0:
160+
; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0
161+
; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
162+
; CHECK-GI-NEXT: ret
81163
%1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
82164
%2 = zext <8 x i8> %1 to <8 x i16>
83165
%tmp = shl <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
84166
ret <8 x i16> %tmp
85167
}
86168

87169
define <4 x i32> @test_ushll2_v8i16(<8 x i16> %a) {
88-
; CHECK: test_ushll2_v8i16:
89-
; CHECK: ushll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #9
170+
; CHECK-SD-LABEL: test_ushll2_v8i16:
171+
; CHECK-SD: // %bb.0:
172+
; CHECK-SD-NEXT: ushll2 v0.4s, v0.8h, #9
173+
; CHECK-SD-NEXT: ret
174+
;
175+
; CHECK-GI-LABEL: test_ushll2_v8i16:
176+
; CHECK-GI: // %bb.0:
177+
; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
178+
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
179+
; CHECK-GI-NEXT: ret
90180
%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
91181
%2 = zext <4 x i16> %1 to <4 x i32>
92182
%tmp = shl <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9>
93183
ret <4 x i32> %tmp
94184
}
95185

96186
define <2 x i64> @test_ushll2_v4i32(<4 x i32> %a) {
97-
; CHECK: test_ushll2_v4i32:
98-
; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #19
187+
; CHECK-SD-LABEL: test_ushll2_v4i32:
188+
; CHECK-SD: // %bb.0:
189+
; CHECK-SD-NEXT: ushll2 v0.2d, v0.4s, #19
190+
; CHECK-SD-NEXT: ret
191+
;
192+
; CHECK-GI-LABEL: test_ushll2_v4i32:
193+
; CHECK-GI: // %bb.0:
194+
; CHECK-GI-NEXT: ushll2 v0.2d, v0.4s, #0
195+
; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
196+
; CHECK-GI-NEXT: ret
99197
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
100198
%2 = zext <2 x i32> %1 to <2 x i64>
101199
%tmp = shl <2 x i64> %2, <i64 19, i64 19>
102200
ret <2 x i64> %tmp
103201
}
104202

105203
define <8 x i16> @test_sshll_shl0_v8i8(<8 x i8> %a) {
106-
; CHECK: test_sshll_shl0_v8i8:
107-
; CHECK: sshll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
204+
; CHECK-LABEL: test_sshll_shl0_v8i8:
205+
; CHECK: // %bb.0:
206+
; CHECK-NEXT: sshll v0.8h, v0.8b, #0
207+
; CHECK-NEXT: ret
108208
%tmp = sext <8 x i8> %a to <8 x i16>
109209
ret <8 x i16> %tmp
110210
}
111211

112212
define <4 x i32> @test_sshll_shl0_v4i16(<4 x i16> %a) {
113-
; CHECK: test_sshll_shl0_v4i16:
114-
; CHECK: sshll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #0
213+
; CHECK-LABEL: test_sshll_shl0_v4i16:
214+
; CHECK: // %bb.0:
215+
; CHECK-NEXT: sshll v0.4s, v0.4h, #0
216+
; CHECK-NEXT: ret
115217
%tmp = sext <4 x i16> %a to <4 x i32>
116218
ret <4 x i32> %tmp
117219
}
118220

119221
define <2 x i64> @test_sshll_shl0_v2i32(<2 x i32> %a) {
120-
; CHECK: test_sshll_shl0_v2i32:
121-
; CHECK: sshll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #0
222+
; CHECK-LABEL: test_sshll_shl0_v2i32:
223+
; CHECK: // %bb.0:
224+
; CHECK-NEXT: sshll v0.2d, v0.2s, #0
225+
; CHECK-NEXT: ret
122226
%tmp = sext <2 x i32> %a to <2 x i64>
123227
ret <2 x i64> %tmp
124228
}
125229

126230
define <8 x i16> @test_ushll_shl0_v8i8(<8 x i8> %a) {
127-
; CHECK: test_ushll_shl0_v8i8:
128-
; CHECK: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
231+
; CHECK-LABEL: test_ushll_shl0_v8i8:
232+
; CHECK: // %bb.0:
233+
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
234+
; CHECK-NEXT: ret
129235
%tmp = zext <8 x i8> %a to <8 x i16>
130236
ret <8 x i16> %tmp
131237
}
132238

133239
define <4 x i32> @test_ushll_shl0_v4i16(<4 x i16> %a) {
134-
; CHECK: test_ushll_shl0_v4i16:
135-
; CHECK: ushll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #0
240+
; CHECK-LABEL: test_ushll_shl0_v4i16:
241+
; CHECK: // %bb.0:
242+
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
243+
; CHECK-NEXT: ret
136244
%tmp = zext <4 x i16> %a to <4 x i32>
137245
ret <4 x i32> %tmp
138246
}
139247

140248
define <2 x i64> @test_ushll_shl0_v2i32(<2 x i32> %a) {
141-
; CHECK: test_ushll_shl0_v2i32:
142-
; CHECK: ushll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #0
249+
; CHECK-LABEL: test_ushll_shl0_v2i32:
250+
; CHECK: // %bb.0:
251+
; CHECK-NEXT: ushll v0.2d, v0.2s, #0
252+
; CHECK-NEXT: ret
143253
%tmp = zext <2 x i32> %a to <2 x i64>
144254
ret <2 x i64> %tmp
145255
}
146256

147257
define <8 x i16> @test_sshll2_shl0_v16i8(<16 x i8> %a) {
148-
; CHECK: test_sshll2_shl0_v16i8:
149-
; CHECK: sshll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #0
258+
; CHECK-LABEL: test_sshll2_shl0_v16i8:
259+
; CHECK: // %bb.0:
260+
; CHECK-NEXT: sshll2 v0.8h, v0.16b, #0
261+
; CHECK-NEXT: ret
150262
%1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
151263
%tmp = sext <8 x i8> %1 to <8 x i16>
152264
ret <8 x i16> %tmp
153265
}
154266

155267
define <4 x i32> @test_sshll2_shl0_v8i16(<8 x i16> %a) {
156-
; CHECK: test_sshll2_shl0_v8i16:
157-
; CHECK: sshll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #0
268+
; CHECK-LABEL: test_sshll2_shl0_v8i16:
269+
; CHECK: // %bb.0:
270+
; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0
271+
; CHECK-NEXT: ret
158272
%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
159273
%tmp = sext <4 x i16> %1 to <4 x i32>
160274
ret <4 x i32> %tmp
161275
}
162276

163277
define <2 x i64> @test_sshll2_shl0_v4i32(<4 x i32> %a) {
164-
; CHECK: test_sshll2_shl0_v4i32:
165-
; CHECK: sshll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #0
278+
; CHECK-LABEL: test_sshll2_shl0_v4i32:
279+
; CHECK: // %bb.0:
280+
; CHECK-NEXT: sshll2 v0.2d, v0.4s, #0
281+
; CHECK-NEXT: ret
166282
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
167283
%tmp = sext <2 x i32> %1 to <2 x i64>
168284
ret <2 x i64> %tmp
169285
}
170286

171287
define <8 x i16> @test_ushll2_shl0_v16i8(<16 x i8> %a) {
172-
; CHECK: test_ushll2_shl0_v16i8:
173-
; CHECK: ushll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #0
288+
; CHECK-LABEL: test_ushll2_shl0_v16i8:
289+
; CHECK: // %bb.0:
290+
; CHECK-NEXT: ushll2 v0.8h, v0.16b, #0
291+
; CHECK-NEXT: ret
174292
%1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
175293
%tmp = zext <8 x i8> %1 to <8 x i16>
176294
ret <8 x i16> %tmp
177295
}
178296

179297
define <4 x i32> @test_ushll2_shl0_v8i16(<8 x i16> %a) {
180-
; CHECK: test_ushll2_shl0_v8i16:
181-
; CHECK: ushll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #0
298+
; CHECK-LABEL: test_ushll2_shl0_v8i16:
299+
; CHECK: // %bb.0:
300+
; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0
301+
; CHECK-NEXT: ret
182302
%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
183303
%tmp = zext <4 x i16> %1 to <4 x i32>
184304
ret <4 x i32> %tmp
185305
}
186306

187307
define <2 x i64> @test_ushll2_shl0_v4i32(<4 x i32> %a) {
188-
; CHECK: test_ushll2_shl0_v4i32:
189-
; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #0
308+
; CHECK-LABEL: test_ushll2_shl0_v4i32:
309+
; CHECK: // %bb.0:
310+
; CHECK-NEXT: ushll2 v0.2d, v0.4s, #0
311+
; CHECK-NEXT: ret
190312
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
191313
%tmp = zext <2 x i32> %1 to <2 x i64>
192314
ret <2 x i64> %tmp
193315
}
194316

195317
define <8 x i16> @test_ushll_cmp(<8 x i8> %a, <8 x i8> %b) #0 {
196-
; CHECK: test_ushll_cmp:
197-
; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
198-
; CHECK-NEXT: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
318+
; CHECK-SD-LABEL: test_ushll_cmp:
319+
; CHECK-SD: // %bb.0:
320+
; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, v1.8b
321+
; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
322+
; CHECK-SD-NEXT: ret
323+
;
324+
; CHECK-GI-LABEL: test_ushll_cmp:
325+
; CHECK-GI: // %bb.0:
326+
; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
327+
; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff
328+
; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
329+
; CHECK-GI-NEXT: shl v0.8h, v0.8h, #15
330+
; CHECK-GI-NEXT: sshr v0.8h, v0.8h, #15
331+
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
332+
; CHECK-GI-NEXT: ret
199333
%cmp.i = icmp eq <8 x i8> %a, %b
200334
%vcgtz.i.i = sext <8 x i1> %cmp.i to <8 x i8>
201335
%vmovl.i.i.i = zext <8 x i8> %vcgtz.i.i to <8 x i16>

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