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‎mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -429,7 +429,7 @@ namespace {
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struct ConvertVectorStore final : OpConversionPattern<vector::StoreOp> {
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using OpConversionPattern::OpConversionPattern;
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ConvertVectorStore(MLIRContext *context, bool useAtomicWrites)
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ConvertVectorStore(MLIRContext *context, bool useAtomicWrites)
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: OpConversionPattern<vector::StoreOp>(context),
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useAtomicWrites_(useAtomicWrites) {}
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@@ -583,8 +583,8 @@ struct ConvertVectorStore final : OpConversionPattern<vector::StoreOp> {
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extractSliceIntoByte(rewriter, loc, valueToStore, 0,
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frontSubWidthStoreElem, *foldedNumFrontPadElems);
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atomicStore(rewriter, loc, memrefBase, currentDestIndex,
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cast<VectorValue>(value), frontMask.getResult());
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subEmulatedWidthStore(rewriter, loc, memrefBase, currentDestIndex,
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cast<VectorValue>(value), frontMask.getResult());
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}
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if (currentSourceIndex >= origElements) {

‎mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned-non-atomic.mlir

Lines changed: 119 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,119 @@
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// RUN: mlir-opt --test-emulate-narrow-int="arith-compute-bitwidth=1 memref-load-bitwidth=8 atomic-store=false" --cse --split-input-file %s | FileCheck %s
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// TODO: remove memref.alloc() in the tests to eliminate noises.
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// memref.alloc exists here because sub-byte vector data types such as i2
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// are currently not supported as input arguments.
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func.func @vector_store_i2_const_index_two_rmw(%arg0: vector<3xi2>) {
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%0 = memref.alloc() : memref<3x3xi2>
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%c0 = arith.constant 0 : index
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%c2 = arith.constant 2 : index
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vector.store %arg0, %0[%c2, %c0] :memref<3x3xi2>, vector<3xi2>
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return
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}
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// Load from bit [12:18), byte [1:2] of total 3 bytes, both bytes needs rmw.
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// CHECK: func @vector_store_i2_const_index_two_rmw(
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// CHECK-SAME: %[[ARG0:.+]]: vector<3xi2>)
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// CHECK: %[[ALLOC:.+]] = memref.alloc() : memref<3xi8>
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// CHECK: %[[C1:.+]] = arith.constant 1 : index
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// Part 1 RMW sequence
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// CHECK: %[[CST:.+]] = arith.constant dense<[false, false, true, true]>
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// CHECK: %[[CST0:.+]] = arith.constant dense<0> : vector<4xi2>
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// CHECK: %[[EXTRACT:.+]] = vector.extract_strided_slice %[[ARG0]]
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// CHECK-SAME: {offsets = [0], sizes = [2], strides = [1]} : vector<3xi2> to vector<2xi2>
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// CHECK: %[[INSERT:.+]] = vector.insert_strided_slice %[[EXTRACT]], %[[CST0]]
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// CHECK-SAME: {offsets = [2], strides = [1]} : vector<2xi2> into vector<4xi2>
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// CHECK: %[[LOAD:.+]] = vector.load
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// CHECK: %[[UPCAST:.+]] = vector.bitcast %[[LOAD]] : vector<1xi8> to vector<4xi2>
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// CHECK: %[[SELECT:.+]] = arith.select %[[CST]], %[[INSERT]], %[[UPCAST]]
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// CHECK: %[[DOWNCAST:.+]] = vector.bitcast %[[SELECT]]
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// CHECK: vector.store %[[DOWNCAST]], %[[ALLOC]][%[[C1]]]
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// Part 2 RMW sequence
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// CHECK: %[[OFFSET:.+]] = arith.addi %[[C1]], %[[C1]] : index
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// CHECK: %[[EXTRACT2:.+]] = vector.extract_strided_slice %[[ARG0]]
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// CHECK-SAME: {offsets = [2], sizes = [1], strides = [1]} : vector<3xi2> to vector<1xi2>
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// CHECK: %[[INSERT2:.+]] = vector.insert_strided_slice %[[EXTRACT2]], %[[CST0]]
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// CHECK-SAME: {offsets = [0], strides = [1]} : vector<1xi2> into vector<4xi2>
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// CHECK: %[[CST1:.+]] = arith.constant dense<[true, false, false, false]> : vector<4xi1>
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// CHECK: %[[LOAD2:.+]] = vector.load
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// CHECK: %[[UPCAST2:.+]] = vector.bitcast %[[LOAD2]] : vector<1xi8> to vector<4xi2>
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// CHECK: %[[SELECT2:.+]] = arith.select %[[CST1]], %[[INSERT2]], %[[UPCAST2]]
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// CHECK: %[[DOWNCAST2:.+]] = vector.bitcast %[[SELECT2]]
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// CHECK: vector.store %[[DOWNCAST2]], %[[ALLOC]][%[[OFFSET]]]
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// -----
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func.func @vector_store_i2_rmw(%arg0: vector<7xi2>) {
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%0 = memref.alloc() : memref<3x7xi2>
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%c0 = arith.constant 0 : index
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%c1 = arith.constant 1 : index
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vector.store %arg0, %0[%c1, %c0] :memref<3x7xi2>, vector<7xi2>
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return
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}
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// CHECK: func @vector_store_i2_rmw(
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// CHECK-SAME: %[[ARG0:.+]]:
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// CHECK: %[[ALLOC:.+]] = memref.alloc() : memref<6xi8>
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// CHECK: %[[C1:.+]] = arith.constant 1 : index
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// CHECK: %[[CST:.+]] = arith.constant dense<[false, false, false, true]>
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// CHECK: %[[CST0:.+]] = arith.constant dense<0> : vector<4xi2>
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// CHECK: %[[EXTRACT:.+]] = vector.extract_strided_slice %[[ARG0]]
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// CHECK-SAME: {offsets = [0], sizes = [1], strides = [1]}
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// CHECK: %[[INSERT:.+]] = vector.insert_strided_slice %[[EXTRACT]], %[[CST0]]
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// CHECK-SAME: {offsets = [3], strides = [1]}
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// First sub-width RMW:
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// CHECK: %[[LOAD:.+]] = vector.load %[[ALLOC]][%[[C1]]]
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// CHECK: %[[UPCAST:.+]] = vector.bitcast %[[LOAD]] : vector<1xi8> to vector<4xi2>
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// CHECK: %[[SELECT:.+]] = arith.select %[[CST]], %[[INSERT]], %[[UPCAST]]
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// CHECK: %[[DOWNCAST:.+]] = vector.bitcast %[[SELECT]]
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// CHECK: vector.store %[[DOWNCAST]], %[[ALLOC]][%[[C1]]]
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// Full-width store:
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// CHECK: %[[INDEX:.+]] = arith.addi %[[C1]], %[[C1]]
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// CHECK: %[[EXTRACT1:.+]] = vector.extract_strided_slice %[[ARG0]]
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// CHECK-SAME: {offsets = [1], sizes = [4], strides = [1]}
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// CHECK: %[[BITCAST:.+]] = vector.bitcast %[[EXTRACT1]]
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// CHECK: vector.store %[[BITCAST]], %[[ALLOC]][%[[INDEX]]]
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// Second sub-width RMW:
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// CHECK: %[[INDEX2:.+]] = arith.addi %[[INDEX]], %[[C1]]
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// CHECK: %[[EXTRACT2:.+]] = vector.extract_strided_slice %[[ARG0]]
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// CHECK-SAME: {offsets = [5], sizes = [2], strides = [1]}
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// CHECK: %[[INSERT2:.+]] = vector.insert_strided_slice %[[EXTRACT2]]
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// CHECK-SAME: {offsets = [0], strides = [1]}
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// CHECK: %[[CST1:.+]] = arith.constant dense<[true, true, false, false]>
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// CHECK: %[[LOAD1:.+]] = vector.load %[[ALLOC]][%[[INDEX2]]]
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// CHECK: %[[UPCAST1:.+]] = vector.bitcast %[[LOAD1]]
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// CHECK: %[[SELECT1:.+]] = arith.select %[[CST1]], %[[INSERT2]], %[[UPCAST1]]
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// CHECK: %[[DOWNCAST1:.+]] = vector.bitcast %[[SELECT1]]
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// CHECK: vector.store %[[DOWNCAST1]], %[[ALLOC]][%[[INDEX2]]]
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// -----
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func.func @vector_store_i2_single_rmw(%arg0: vector<1xi2>) {
98+
%0 = memref.alloc() : memref<4x1xi2>
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%c0 = arith.constant 0 : index
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%c1 = arith.constant 1 : index
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vector.store %arg0, %0[%c1, %c0] :memref<4x1xi2>, vector<1xi2>
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return
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}
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// in this test, only emit 1 rmw store
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// CHECK: func @vector_store_i2_single_rmw(
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// CHECK-SAME: %[[ARG0:.+]]: vector<1xi2>)
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// CHECK: %[[ALLOC:.+]] = memref.alloc() : memref<1xi8>
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// CHECK: %[[C0:.+]] = arith.constant 0 : index
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// CHECK: %[[CST:.+]] = arith.constant dense<[false, true, false, false]>
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// CHECK: %[[CST0:.+]] = arith.constant dense<0> : vector<4xi2>
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// CHECK: %[[INSERT:.+]] = vector.insert_strided_slice %[[ARG0]], %[[CST0]]
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// CHECK-SAME: {offsets = [1], strides = [1]} : vector<1xi2> into vector<4xi2>
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// CHECK: %[[LOAD:.+]] = vector.load %[[ALLOC]][%[[C0]]] : memref<1xi8>, vector<1xi8>
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// CHECK: %[[UPCAST:.+]] = vector.bitcast %[[LOAD]] : vector<1xi8> to vector<4xi2>
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// CHECK: %[[SELECT:.+]] = arith.select %[[CST]], %[[INSERT]], %[[UPCAST]]
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// CHECK: %[[DOWNCAST:.+]] = vector.bitcast %[[SELECT]]
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// CHECK: vector.store %[[DOWNCAST]], %[[ALLOC]][%[[C0]]]
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