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[X86][RA] Add two address hints for compressible NDD instructions. (#98603)
To address @topperc 's comment at https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/5?u=kanrobert
1 parent 8ec3049 commit f301887

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14 files changed

+846
-785
lines changed

14 files changed

+846
-785
lines changed

‎llvm/include/llvm/CodeGen/TargetRegisterInfo.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -630,6 +630,12 @@ class TargetRegisterInfo : public MCRegisterInfo {
630630
return false;
631631
}
632632

633+
/// Returns true if RC is a class/subclass of general purpose register.
634+
virtual bool
635+
isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
636+
return false;
637+
}
638+
633639
/// Prior to adding the live-out mask to a stackmap or patchpoint
634640
/// instruction, provide the target the opportunity to adjust it (mainly to
635641
/// remove pseudo-registers that should be ignored).

‎llvm/lib/Target/X86/X86DomainReassignment.cpp

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -41,21 +41,14 @@ static cl::opt<bool> DisableX86DomainReassignment(
4141
namespace {
4242
enum RegDomain { NoDomain = -1, GPRDomain, MaskDomain, OtherDomain, NumDomains };
4343

44-
static bool isGPR(const TargetRegisterClass *RC) {
45-
return X86::GR64RegClass.hasSubClassEq(RC) ||
46-
X86::GR32RegClass.hasSubClassEq(RC) ||
47-
X86::GR16RegClass.hasSubClassEq(RC) ||
48-
X86::GR8RegClass.hasSubClassEq(RC);
49-
}
50-
5144
static bool isMask(const TargetRegisterClass *RC,
5245
const TargetRegisterInfo *TRI) {
5346
return X86::VK16RegClass.hasSubClassEq(RC);
5447
}
5548

5649
static RegDomain getDomain(const TargetRegisterClass *RC,
5750
const TargetRegisterInfo *TRI) {
58-
if (isGPR(RC))
51+
if (TRI->isGeneralPurposeRegisterClass(RC))
5952
return GPRDomain;
6053
if (isMask(RC, TRI))
6154
return MaskDomain;
@@ -797,7 +790,8 @@ bool X86DomainReassignment::runOnMachineFunction(MachineFunction &MF) {
797790
continue;
798791

799792
// GPR only current source domain supported.
800-
if (!isGPR(MRI->getRegClass(Reg)))
793+
if (!MRI->getTargetRegisterInfo()->isGeneralPurposeRegisterClass(
794+
MRI->getRegClass(Reg)))
801795
continue;
802796

803797
// Register already in closure.

‎llvm/lib/Target/X86/X86RegisterInfo.cpp

Lines changed: 54 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,12 @@ static cl::opt<bool>
4545
EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
4646
cl::desc("Enable use of a base pointer for complex stack frames"));
4747

48+
static cl::opt<bool>
49+
DisableRegAllocNDDHints("x86-disable-regalloc-hints-for-ndd", cl::Hidden,
50+
cl::init(false),
51+
cl::desc("Disable two address hints for register "
52+
"allocation"));
53+
4854
X86RegisterInfo::X86RegisterInfo(const Triple &TT)
4955
: X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
5056
X86_MC::getDwarfRegFlavour(TT, false),
@@ -1080,10 +1086,57 @@ bool X86RegisterInfo::getRegAllocationHints(Register VirtReg,
10801086
const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
10811087
bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
10821088
VirtReg, Order, Hints, MF, VRM, Matrix);
1089+
const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
1090+
const TargetRegisterInfo &TRI = *ST.getRegisterInfo();
10831091

10841092
unsigned ID = RC.getID();
1085-
if (ID != X86::TILERegClassID)
1093+
1094+
if (!VRM)
1095+
return BaseImplRetVal;
1096+
1097+
if (ID != X86::TILERegClassID) {
1098+
if (DisableRegAllocNDDHints || !ST.hasNDD() ||
1099+
!TRI.isGeneralPurposeRegisterClass(&RC))
1100+
return BaseImplRetVal;
1101+
1102+
// Add any two address hints after any copy hints.
1103+
SmallSet<unsigned, 4> TwoAddrHints;
1104+
1105+
auto TryAddNDDHint = [&](const MachineOperand &MO) {
1106+
Register Reg = MO.getReg();
1107+
Register PhysReg =
1108+
Register::isPhysicalRegister(Reg) ? Reg : Register(VRM->getPhys(Reg));
1109+
if (PhysReg && !MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
1110+
TwoAddrHints.insert(PhysReg);
1111+
};
1112+
1113+
// NDD instructions is compressible when Op0 is allocated to the same
1114+
// physic register as Op1 (or Op2 if it's commutable).
1115+
for (auto &MO : MRI->reg_nodbg_operands(VirtReg)) {
1116+
const MachineInstr &MI = *MO.getParent();
1117+
if (!X86::getNonNDVariant(MI.getOpcode()))
1118+
continue;
1119+
unsigned OpIdx = MI.getOperandNo(&MO);
1120+
if (OpIdx == 0) {
1121+
assert(MI.getOperand(1).isReg());
1122+
TryAddNDDHint(MI.getOperand(1));
1123+
if (MI.isCommutable()) {
1124+
assert(MI.getOperand(2).isReg());
1125+
TryAddNDDHint(MI.getOperand(2));
1126+
}
1127+
} else if (OpIdx == 1) {
1128+
TryAddNDDHint(MI.getOperand(0));
1129+
} else if (MI.isCommutable() && OpIdx == 2) {
1130+
TryAddNDDHint(MI.getOperand(0));
1131+
}
1132+
}
1133+
1134+
for (MCPhysReg OrderReg : Order)
1135+
if (TwoAddrHints.count(OrderReg))
1136+
Hints.push_back(OrderReg);
1137+
10861138
return BaseImplRetVal;
1139+
}
10871140

10881141
ShapeT VirtShape = getTileShape(VirtReg, const_cast<VirtRegMap *>(VRM), MRI);
10891142
auto AddHint = [&](MCPhysReg PhysReg) {

‎llvm/test/CodeGen/X86/apx/and.ll

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -482,17 +482,17 @@ define i1 @andflag16rr(i16 %a, i16 %b) {
482482
define i1 @andflag32rr(i32 %a, i32 %b) {
483483
; CHECK-LABEL: andflag32rr:
484484
; CHECK: # %bb.0:
485-
; CHECK-NEXT: andl %esi, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x21,0xf7]
485+
; CHECK-NEXT: andl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x21,0xfe]
486486
; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
487-
; CHECK-NEXT: movl %ecx, d64(%rip) # encoding: [0x89,0x0d,A,A,A,A]
487+
; CHECK-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
488488
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
489489
; CHECK-NEXT: retq # encoding: [0xc3]
490490
;
491491
; NF-LABEL: andflag32rr:
492492
; NF: # %bb.0:
493-
; NF-NEXT: andl %esi, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x21,0xf7]
493+
; NF-NEXT: andl %edi, %esi # EVEX TO LEGACY Compression encoding: [0x21,0xfe]
494494
; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
495-
; NF-NEXT: movl %ecx, d64(%rip) # encoding: [0x89,0x0d,A,A,A,A]
495+
; NF-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
496496
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
497497
; NF-NEXT: retq # encoding: [0xc3]
498498
%v0 = and i32 %a, %b ; 0xff << 50
@@ -504,17 +504,17 @@ define i1 @andflag32rr(i32 %a, i32 %b) {
504504
define i1 @andflag64rr(i64 %a, i64 %b) {
505505
; CHECK-LABEL: andflag64rr:
506506
; CHECK: # %bb.0:
507-
; CHECK-NEXT: andq %rsi, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x21,0xf7]
507+
; CHECK-NEXT: andq %rdi, %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xfe]
508508
; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
509-
; CHECK-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
509+
; CHECK-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
510510
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
511511
; CHECK-NEXT: retq # encoding: [0xc3]
512512
;
513513
; NF-LABEL: andflag64rr:
514514
; NF: # %bb.0:
515-
; NF-NEXT: andq %rsi, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x21,0xf7]
515+
; NF-NEXT: andq %rdi, %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x21,0xfe]
516516
; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
517-
; NF-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
517+
; NF-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
518518
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
519519
; NF-NEXT: retq # encoding: [0xc3]
520520
%v0 = and i64 %a, %b ; 0xff << 50
@@ -578,17 +578,17 @@ define i1 @andflag16rm(ptr %ptr, i16 %b) {
578578
define i1 @andflag32rm(ptr %ptr, i32 %b) {
579579
; CHECK-LABEL: andflag32rm:
580580
; CHECK: # %bb.0:
581-
; CHECK-NEXT: andl (%rdi), %esi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x23,0x37]
581+
; CHECK-NEXT: andl (%rdi), %esi # EVEX TO LEGACY Compression encoding: [0x23,0x37]
582582
; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
583-
; CHECK-NEXT: movl %ecx, d64(%rip) # encoding: [0x89,0x0d,A,A,A,A]
583+
; CHECK-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
584584
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
585585
; CHECK-NEXT: retq # encoding: [0xc3]
586586
;
587587
; NF-LABEL: andflag32rm:
588588
; NF: # %bb.0:
589-
; NF-NEXT: andl (%rdi), %esi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x23,0x37]
589+
; NF-NEXT: andl (%rdi), %esi # EVEX TO LEGACY Compression encoding: [0x23,0x37]
590590
; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
591-
; NF-NEXT: movl %ecx, d64(%rip) # encoding: [0x89,0x0d,A,A,A,A]
591+
; NF-NEXT: movl %esi, d64(%rip) # encoding: [0x89,0x35,A,A,A,A]
592592
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
593593
; NF-NEXT: retq # encoding: [0xc3]
594594
%a = load i32, ptr %ptr
@@ -601,17 +601,17 @@ define i1 @andflag32rm(ptr %ptr, i32 %b) {
601601
define i1 @andflag64rm(ptr %ptr, i64 %b) {
602602
; CHECK-LABEL: andflag64rm:
603603
; CHECK: # %bb.0:
604-
; CHECK-NEXT: andq (%rdi), %rsi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x23,0x37]
604+
; CHECK-NEXT: andq (%rdi), %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x23,0x37]
605605
; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
606-
; CHECK-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
606+
; CHECK-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
607607
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
608608
; CHECK-NEXT: retq # encoding: [0xc3]
609609
;
610610
; NF-LABEL: andflag64rm:
611611
; NF: # %bb.0:
612-
; NF-NEXT: andq (%rdi), %rsi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x23,0x37]
612+
; NF-NEXT: andq (%rdi), %rsi # EVEX TO LEGACY Compression encoding: [0x48,0x23,0x37]
613613
; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
614-
; NF-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
614+
; NF-NEXT: movq %rsi, d64(%rip) # encoding: [0x48,0x89,0x35,A,A,A,A]
615615
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
616616
; NF-NEXT: retq # encoding: [0xc3]
617617
%a = load i64, ptr %ptr
@@ -672,19 +672,19 @@ define i1 @andflag16ri(i16 %a) {
672672
define i1 @andflag32ri(i32 %a) {
673673
; CHECK-LABEL: andflag32ri:
674674
; CHECK: # %bb.0:
675-
; CHECK-NEXT: andl $123456, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x81,0xe7,0x40,0xe2,0x01,0x00]
675+
; CHECK-NEXT: andl $123456, %edi # EVEX TO LEGACY Compression encoding: [0x81,0xe7,0x40,0xe2,0x01,0x00]
676676
; CHECK-NEXT: # imm = 0x1E240
677677
; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
678-
; CHECK-NEXT: movl %ecx, d64(%rip) # encoding: [0x89,0x0d,A,A,A,A]
678+
; CHECK-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
679679
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
680680
; CHECK-NEXT: retq # encoding: [0xc3]
681681
;
682682
; NF-LABEL: andflag32ri:
683683
; NF: # %bb.0:
684-
; NF-NEXT: andl $123456, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x81,0xe7,0x40,0xe2,0x01,0x00]
684+
; NF-NEXT: andl $123456, %edi # EVEX TO LEGACY Compression encoding: [0x81,0xe7,0x40,0xe2,0x01,0x00]
685685
; NF-NEXT: # imm = 0x1E240
686686
; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
687-
; NF-NEXT: movl %ecx, d64(%rip) # encoding: [0x89,0x0d,A,A,A,A]
687+
; NF-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
688688
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
689689
; NF-NEXT: retq # encoding: [0xc3]
690690
%v0 = and i32 %a, 123456 ; 0xff << 50
@@ -696,19 +696,19 @@ define i1 @andflag32ri(i32 %a) {
696696
define i1 @andflag64ri(i64 %a) {
697697
; CHECK-LABEL: andflag64ri:
698698
; CHECK: # %bb.0:
699-
; CHECK-NEXT: andq $123456, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x81,0xe7,0x40,0xe2,0x01,0x00]
699+
; CHECK-NEXT: andq $123456, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xe7,0x40,0xe2,0x01,0x00]
700700
; CHECK-NEXT: # imm = 0x1E240
701701
; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
702-
; CHECK-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
702+
; CHECK-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
703703
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
704704
; CHECK-NEXT: retq # encoding: [0xc3]
705705
;
706706
; NF-LABEL: andflag64ri:
707707
; NF: # %bb.0:
708-
; NF-NEXT: andq $123456, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x81,0xe7,0x40,0xe2,0x01,0x00]
708+
; NF-NEXT: andq $123456, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x81,0xe7,0x40,0xe2,0x01,0x00]
709709
; NF-NEXT: # imm = 0x1E240
710710
; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
711-
; NF-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
711+
; NF-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
712712
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
713713
; NF-NEXT: retq # encoding: [0xc3]
714714
%v0 = and i64 %a, 123456 ; 0xff << 50
@@ -743,17 +743,17 @@ define i1 @andflag16ri8(i16 %a) {
743743
define i1 @andflag32ri8(i32 %a) {
744744
; CHECK-LABEL: andflag32ri8:
745745
; CHECK: # %bb.0:
746-
; CHECK-NEXT: andl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x83,0xe7,0x7b]
746+
; CHECK-NEXT: andl $123, %edi # EVEX TO LEGACY Compression encoding: [0x83,0xe7,0x7b]
747747
; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
748-
; CHECK-NEXT: movl %ecx, d64(%rip) # encoding: [0x89,0x0d,A,A,A,A]
748+
; CHECK-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
749749
; CHECK-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
750750
; CHECK-NEXT: retq # encoding: [0xc3]
751751
;
752752
; NF-LABEL: andflag32ri8:
753753
; NF: # %bb.0:
754-
; NF-NEXT: andl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x83,0xe7,0x7b]
754+
; NF-NEXT: andl $123, %edi # EVEX TO LEGACY Compression encoding: [0x83,0xe7,0x7b]
755755
; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
756-
; NF-NEXT: movl %ecx, d64(%rip) # encoding: [0x89,0x0d,A,A,A,A]
756+
; NF-NEXT: movl %edi, d64(%rip) # encoding: [0x89,0x3d,A,A,A,A]
757757
; NF-NEXT: # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
758758
; NF-NEXT: retq # encoding: [0xc3]
759759
%v0 = and i32 %a, 123 ; 0xff << 50
@@ -765,17 +765,17 @@ define i1 @andflag32ri8(i32 %a) {
765765
define i1 @andflag64ri8(i64 %a) {
766766
; CHECK-LABEL: andflag64ri8:
767767
; CHECK: # %bb.0:
768-
; CHECK-NEXT: andq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x83,0xe7,0x7b]
768+
; CHECK-NEXT: andq $123, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xe7,0x7b]
769769
; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
770-
; CHECK-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
770+
; CHECK-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
771771
; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
772772
; CHECK-NEXT: retq # encoding: [0xc3]
773773
;
774774
; NF-LABEL: andflag64ri8:
775775
; NF: # %bb.0:
776-
; NF-NEXT: andq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x83,0xe7,0x7b]
776+
; NF-NEXT: andq $123, %rdi # EVEX TO LEGACY Compression encoding: [0x48,0x83,0xe7,0x7b]
777777
; NF-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
778-
; NF-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
778+
; NF-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A]
779779
; NF-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
780780
; NF-NEXT: retq # encoding: [0xc3]
781781
%v0 = and i64 %a, 123 ; 0xff << 50

‎llvm/test/CodeGen/X86/apx/cmov.ll

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,10 @@ define i8 @cmov8(i8 %a, i8 %b, i8 %x, ptr %y.ptr) {
55
; CHECK-LABEL: cmov8:
66
; CHECK: # %bb.0: # %entry
77
; CHECK-NEXT: cmpb %sil, %dil # encoding: [0x40,0x38,0xf7]
8-
; CHECK-NEXT: cmoval %edi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x47,0xd7]
9-
; CHECK-NEXT: movzbl (%rcx), %ecx # encoding: [0x0f,0xb6,0x09]
10-
; CHECK-NEXT: cmovbel %edx, %ecx # EVEX TO LEGACY Compression encoding: [0x0f,0x46,0xca]
11-
; CHECK-NEXT: addb %cl, %al # EVEX TO LEGACY Compression encoding: [0x00,0xc8]
8+
; CHECK-NEXT: cmovbel %edx, %edi # EVEX TO LEGACY Compression encoding: [0x0f,0x46,0xfa]
9+
; CHECK-NEXT: movzbl (%rcx), %eax # encoding: [0x0f,0xb6,0x01]
10+
; CHECK-NEXT: cmovbel %edx, %eax # EVEX TO LEGACY Compression encoding: [0x0f,0x46,0xc2]
11+
; CHECK-NEXT: addb %dil, %al # EVEX TO LEGACY Compression encoding: [0x40,0x00,0xf8]
1212
; CHECK-NEXT: retq # encoding: [0xc3]
1313
entry:
1414
%cond = icmp ugt i8 %a, %b
@@ -23,9 +23,9 @@ define i16 @cmov16(i16 %a, i16 %b, i16 %x, ptr %y.ptr) {
2323
; CHECK-LABEL: cmov16:
2424
; CHECK: # %bb.0: # %entry
2525
; CHECK-NEXT: cmpw %si, %di # encoding: [0x66,0x39,0xf7]
26-
; CHECK-NEXT: cmoval %edi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x47,0xd7]
27-
; CHECK-NEXT: cmovaw (%rcx), %dx, %cx # encoding: [0x62,0xf4,0x75,0x18,0x47,0x11]
28-
; CHECK-NEXT: addw %cx, %ax # EVEX TO LEGACY Compression encoding: [0x66,0x01,0xc8]
26+
; CHECK-NEXT: cmovbel %edx, %edi # EVEX TO LEGACY Compression encoding: [0x0f,0x46,0xfa]
27+
; CHECK-NEXT: cmovaw (%rcx), %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x47,0x11]
28+
; CHECK-NEXT: addw %di, %ax # EVEX TO LEGACY Compression encoding: [0x66,0x01,0xf8]
2929
; CHECK-NEXT: retq # encoding: [0xc3]
3030
entry:
3131
%cond = icmp ugt i16 %a, %b
@@ -41,8 +41,8 @@ define i32 @cmov32(i32 %a, i32 %b, i32 %x, ptr %y.ptr) {
4141
; CHECK: # %bb.0: # %entry
4242
; CHECK-NEXT: cmpl %esi, %edi # encoding: [0x39,0xf7]
4343
; CHECK-NEXT: cmoval %edi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x47,0xd7]
44-
; CHECK-NEXT: cmoval (%rcx), %edx, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x47,0x11]
45-
; CHECK-NEXT: addl %ecx, %eax # EVEX TO LEGACY Compression encoding: [0x01,0xc8]
44+
; CHECK-NEXT: cmoval (%rcx), %edx # EVEX TO LEGACY Compression encoding: [0x0f,0x47,0x11]
45+
; CHECK-NEXT: addl %edx, %eax # EVEX TO LEGACY Compression encoding: [0x01,0xd0]
4646
; CHECK-NEXT: retq # encoding: [0xc3]
4747
entry:
4848
%cond = icmp ugt i32 %a, %b
@@ -58,8 +58,8 @@ define i64 @cmov64(i64 %a, i64 %b, i64 %x, ptr %y.ptr) {
5858
; CHECK: # %bb.0: # %entry
5959
; CHECK-NEXT: cmpq %rsi, %rdi # encoding: [0x48,0x39,0xf7]
6060
; CHECK-NEXT: cmovaq %rdi, %rdx, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x47,0xd7]
61-
; CHECK-NEXT: cmovaq (%rcx), %rdx, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x47,0x11]
62-
; CHECK-NEXT: addq %rcx, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x01,0xc8]
61+
; CHECK-NEXT: cmovaq (%rcx), %rdx # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0x47,0x11]
62+
; CHECK-NEXT: addq %rdx, %rax # EVEX TO LEGACY Compression encoding: [0x48,0x01,0xd0]
6363
; CHECK-NEXT: retq # encoding: [0xc3]
6464
entry:
6565
%cond = icmp ugt i64 %a, %b

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