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1 parent 5cfd041 commit f38c31dCopy full SHA for f38c31d
llvm/docs/GlobalISel/GenericOpcode.rst
@@ -760,7 +760,8 @@ Create a scalable vector where all lanes are linear sequences starting at 0
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with a given unsigned step.
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The type of the operand must be equal to the vector element type. Arithmetic
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-is performed modulo the bitwidth of the element.
+is performed modulo the bitwidth of the element. The step must be > 0.
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+Otherwise the vector is zero. The canonical is splat vector of zeros.
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.. code-block::
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