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[VectorCombine][test] Supplement tests of the load-extractelement sequence (#65442)
The newly added tests are all about scalable vector types.
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‎llvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll

Lines changed: 151 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,17 @@ define i32 @load_extract_idx_0(ptr %x) {
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ret i32 %r
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}
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define i32 @vscale_load_extract_idx_0(ptr %x) {
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; CHECK-LABEL: @vscale_load_extract_idx_0(
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; CHECK-NEXT: [[LV:%.*]] = load <vscale x 4 x i32>, ptr [[X:%.*]], align 16
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; CHECK-NEXT: [[R:%.*]] = extractelement <vscale x 4 x i32> [[LV]], i32 0
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; CHECK-NEXT: ret i32 [[R]]
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;
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%lv = load <vscale x 4 x i32>, ptr %x
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%r = extractelement <vscale x 4 x i32> %lv, i32 0
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ret i32 %r
25+
}
26+
1627
; If the original load had a smaller alignment than the scalar type, the
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; smaller alignment should be used.
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define i32 @load_extract_idx_0_small_alignment(ptr %x) {
@@ -48,6 +59,17 @@ define i32 @load_extract_idx_2(ptr %x) {
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ret i32 %r
4960
}
5061

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define i32 @vscale_load_extract_idx_2(ptr %x) {
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; CHECK-LABEL: @vscale_load_extract_idx_2(
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; CHECK-NEXT: [[LV:%.*]] = load <vscale x 4 x i32>, ptr [[X:%.*]], align 16
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; CHECK-NEXT: [[R:%.*]] = extractelement <vscale x 4 x i32> [[LV]], i32 2
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; CHECK-NEXT: ret i32 [[R]]
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;
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%lv = load <vscale x 4 x i32>, ptr %x
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%r = extractelement <vscale x 4 x i32> %lv, i32 2
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ret i32 %r
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}
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5173
define i32 @load_extract_idx_3(ptr %x) {
5274
; CHECK-LABEL: @load_extract_idx_3(
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds <4 x i32>, ptr [[X:%.*]], i32 0, i32 3
@@ -72,6 +94,17 @@ define i32 @load_extract_idx_4(ptr %x) {
7294
ret i32 %r
7395
}
7496

97+
define i32 @vscale_load_extract_idx_4(ptr %x) {
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; CHECK-LABEL: @vscale_load_extract_idx_4(
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; CHECK-NEXT: [[LV:%.*]] = load <vscale x 4 x i32>, ptr [[X:%.*]], align 16
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; CHECK-NEXT: [[R:%.*]] = extractelement <vscale x 4 x i32> [[LV]], i32 4
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; CHECK-NEXT: ret i32 [[R]]
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;
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%lv = load <vscale x 4 x i32>, ptr %x
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%r = extractelement <vscale x 4 x i32> %lv, i32 4
105+
ret i32 %r
106+
}
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75108
define i32 @load_extract_idx_var_i64(ptr %x, i64 %idx) {
76109
; CHECK-LABEL: @load_extract_idx_var_i64(
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; CHECK-NEXT: [[LV:%.*]] = load <4 x i32>, ptr [[X:%.*]], align 16
@@ -104,6 +137,25 @@ entry:
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ret i32 %r
105138
}
106139

140+
define i32 @vscale_load_extract_idx_var_i64_known_valid_by_assume(ptr %x, i64 %idx) {
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; CHECK-LABEL: @vscale_load_extract_idx_var_i64_known_valid_by_assume(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[IDX:%.*]], 4
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; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
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; CHECK-NEXT: [[LV:%.*]] = load <vscale x 4 x i32>, ptr [[X:%.*]], align 16
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; CHECK-NEXT: call void @maythrow()
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; CHECK-NEXT: [[R:%.*]] = extractelement <vscale x 4 x i32> [[LV]], i64 [[IDX]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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entry:
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%cmp = icmp ult i64 %idx, 4
152+
call void @llvm.assume(i1 %cmp)
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%lv = load <vscale x 4 x i32>, ptr %x
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call void @maythrow()
155+
%r = extractelement <vscale x 4 x i32> %lv, i64 %idx
156+
ret i32 %r
157+
}
158+
107159
declare i1 @cond()
108160

109161
define i32 @load_extract_idx_var_i64_known_valid_by_assume_in_dominating_block(ptr %x, i64 %idx, i1 %c.1) {
@@ -213,6 +265,45 @@ entry:
213265
ret i32 %r
214266
}
215267

268+
define i32 @vscale_load_extract_idx_var_i64_not_known_valid_by_assume_0(ptr %x, i64 %idx) {
269+
; CHECK-LABEL: @vscale_load_extract_idx_var_i64_not_known_valid_by_assume_0(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[IDX:%.*]], 5
272+
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
273+
; CHECK-NEXT: [[LV:%.*]] = load <vscale x 4 x i32>, ptr [[X:%.*]], align 16
274+
; CHECK-NEXT: [[R:%.*]] = extractelement <vscale x 4 x i32> [[LV]], i64 [[IDX]]
275+
; CHECK-NEXT: ret i32 [[R]]
276+
;
277+
entry:
278+
%cmp = icmp ult i64 %idx, 5
279+
call void @llvm.assume(i1 %cmp)
280+
%lv = load <vscale x 4 x i32>, ptr %x
281+
%r = extractelement <vscale x 4 x i32> %lv, i64 %idx
282+
ret i32 %r
283+
}
284+
285+
define i32 @vscale_load_extract_idx_var_i64_not_known_valid_by_assume_1(ptr %x, i64 %idx) {
286+
; CHECK-LABEL: @vscale_load_extract_idx_var_i64_not_known_valid_by_assume_1(
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; CHECK-NEXT: entry:
288+
; CHECK-NEXT: [[VS:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[VM:%.*]] = mul i64 [[VS]], 4
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; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[IDX:%.*]], [[VM]]
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; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
292+
; CHECK-NEXT: [[LV:%.*]] = load <vscale x 4 x i32>, ptr [[X:%.*]], align 16
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; CHECK-NEXT: [[R:%.*]] = extractelement <vscale x 4 x i32> [[LV]], i64 [[IDX]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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entry:
297+
%vs = call i64 @llvm.vscale.i64()
298+
%vm = mul i64 %vs, 4
299+
%cmp = icmp ult i64 %idx, %vm
300+
call void @llvm.assume(i1 %cmp)
301+
%lv = load <vscale x 4 x i32>, ptr %x
302+
%r = extractelement <vscale x 4 x i32> %lv, i64 %idx
303+
ret i32 %r
304+
}
305+
306+
declare i64 @llvm.vscale.i64()
216307
declare void @llvm.assume(i1)
217308

218309
define i32 @load_extract_idx_var_i64_known_valid_by_and(ptr %x, i64 %idx) {
@@ -230,6 +321,21 @@ entry:
230321
ret i32 %r
231322
}
232323

324+
define i32 @vscale_load_extract_idx_var_i64_known_valid_by_and(ptr %x, i64 %idx) {
325+
; CHECK-LABEL: @vscale_load_extract_idx_var_i64_known_valid_by_and(
326+
; CHECK-NEXT: entry:
327+
; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = and i64 [[IDX:%.*]], 3
328+
; CHECK-NEXT: [[LV:%.*]] = load <vscale x 4 x i32>, ptr [[X:%.*]], align 16
329+
; CHECK-NEXT: [[R:%.*]] = extractelement <vscale x 4 x i32> [[LV]], i64 [[IDX_CLAMPED]]
330+
; CHECK-NEXT: ret i32 [[R]]
331+
;
332+
entry:
333+
%idx.clamped = and i64 %idx, 3
334+
%lv = load <vscale x 4 x i32>, ptr %x
335+
%r = extractelement <vscale x 4 x i32> %lv, i64 %idx.clamped
336+
ret i32 %r
337+
}
338+
233339
define i32 @load_extract_idx_var_i64_known_valid_by_and_noundef(ptr %x, i64 noundef %idx) {
234340
; CHECK-LABEL: @load_extract_idx_var_i64_known_valid_by_and_noundef(
235341
; CHECK-NEXT: entry:
@@ -260,6 +366,21 @@ entry:
260366
ret i32 %r
261367
}
262368

369+
define i32 @vscale_load_extract_idx_var_i64_not_known_valid_by_and(ptr %x, i64 %idx) {
370+
; CHECK-LABEL: @vscale_load_extract_idx_var_i64_not_known_valid_by_and(
371+
; CHECK-NEXT: entry:
372+
; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = and i64 [[IDX:%.*]], 4
373+
; CHECK-NEXT: [[LV:%.*]] = load <vscale x 4 x i32>, ptr [[X:%.*]], align 16
374+
; CHECK-NEXT: [[R:%.*]] = extractelement <vscale x 4 x i32> [[LV]], i64 [[IDX_CLAMPED]]
375+
; CHECK-NEXT: ret i32 [[R]]
376+
;
377+
entry:
378+
%idx.clamped = and i64 %idx, 4
379+
%lv = load <vscale x 4 x i32>, ptr %x
380+
%r = extractelement <vscale x 4 x i32> %lv, i64 %idx.clamped
381+
ret i32 %r
382+
}
383+
263384
define i32 @load_extract_idx_var_i64_known_valid_by_urem(ptr %x, i64 %idx) {
264385
; CHECK-LABEL: @load_extract_idx_var_i64_known_valid_by_urem(
265386
; CHECK-NEXT: entry:
@@ -275,6 +396,21 @@ entry:
275396
ret i32 %r
276397
}
277398

399+
define i32 @vscale_load_extract_idx_var_i64_known_valid_by_urem(ptr %x, i64 %idx) {
400+
; CHECK-LABEL: @vscale_load_extract_idx_var_i64_known_valid_by_urem(
401+
; CHECK-NEXT: entry:
402+
; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = urem i64 [[IDX:%.*]], 4
403+
; CHECK-NEXT: [[LV:%.*]] = load <vscale x 4 x i32>, ptr [[X:%.*]], align 16
404+
; CHECK-NEXT: [[R:%.*]] = extractelement <vscale x 4 x i32> [[LV]], i64 [[IDX_CLAMPED]]
405+
; CHECK-NEXT: ret i32 [[R]]
406+
;
407+
entry:
408+
%idx.clamped = urem i64 %idx, 4
409+
%lv = load <vscale x 4 x i32>, ptr %x
410+
%r = extractelement <vscale x 4 x i32> %lv, i64 %idx.clamped
411+
ret i32 %r
412+
}
413+
278414
define i32 @load_extract_idx_var_i64_known_valid_by_urem_noundef(ptr %x, i64 noundef %idx) {
279415
; CHECK-LABEL: @load_extract_idx_var_i64_known_valid_by_urem_noundef(
280416
; CHECK-NEXT: entry:
@@ -305,6 +441,21 @@ entry:
305441
ret i32 %r
306442
}
307443

444+
define i32 @vscale_load_extract_idx_var_i64_not_known_valid_by_urem(ptr %x, i64 %idx) {
445+
; CHECK-LABEL: @vscale_load_extract_idx_var_i64_not_known_valid_by_urem(
446+
; CHECK-NEXT: entry:
447+
; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = urem i64 [[IDX:%.*]], 5
448+
; CHECK-NEXT: [[LV:%.*]] = load <vscale x 4 x i32>, ptr [[X:%.*]], align 16
449+
; CHECK-NEXT: [[R:%.*]] = extractelement <vscale x 4 x i32> [[LV]], i64 [[IDX_CLAMPED]]
450+
; CHECK-NEXT: ret i32 [[R]]
451+
;
452+
entry:
453+
%idx.clamped = urem i64 %idx, 5
454+
%lv = load <vscale x 4 x i32>, ptr %x
455+
%r = extractelement <vscale x 4 x i32> %lv, i64 %idx.clamped
456+
ret i32 %r
457+
}
458+
308459
define i32 @load_extract_idx_var_i32(ptr %x, i32 %idx) {
309460
; CHECK-LABEL: @load_extract_idx_var_i32(
310461
; CHECK-NEXT: [[LV:%.*]] = load <4 x i32>, ptr [[X:%.*]], align 16

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