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[X86][MC] Support enc/dec for SETZUCC and promoted SETCC. (#86473)
apx-spec: https://cdrdv2.intel.com/v1/dl/getContent/784266 apx-syntax-recommendation: https://cdrdv2.intel.com/v1/dl/getContent/817241
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16 files changed

+736
-20
lines changed

16 files changed

+736
-20
lines changed

‎llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3287,6 +3287,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
32873287

32883288
// FIXME: Hack to recognize setneb as setne.
32893289
if (PatchedName.starts_with("set") && PatchedName.ends_with("b") &&
3290+
PatchedName != "setzub" && PatchedName != "setzunb" &&
32903291
PatchedName != "setb" && PatchedName != "setnb")
32913292
PatchedName = PatchedName.substr(0, Name.size()-1);
32923293

‎llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1155,6 +1155,7 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
11551155
Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg);
11561156
break;
11571157
}
1158+
case X86II::MRMXmCC:
11581159
case X86II::MRM0m:
11591160
case X86II::MRM1m:
11601161
case X86II::MRM2m:
@@ -1282,6 +1283,7 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
12821283
Prefix.setRR2(MI, CurOp++);
12831284
break;
12841285
}
1286+
case X86II::MRMXrCC:
12851287
case X86II::MRM0r:
12861288
case X86II::MRM1r:
12871289
case X86II::MRM2r:

‎llvm/lib/Target/X86/X86InstrAsmAlias.td

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -760,7 +760,7 @@ def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm),
760760
def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}",
761761
(MMX_MOVQ64rr_REV VR64:$dst, VR64:$src), 0>;
762762

763-
// CMOV SETCC Aliases
763+
// CMOV SETCC SETZUCC Aliases
764764
multiclass CMOV_SETCC_Aliases<string Cond, int CC> {
765765
def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",
766766
(CMOV16rr GR16:$dst, GR16:$src, CC), 0>;
@@ -787,8 +787,12 @@ let Predicates = [In64BitMode] in {
787787
(CMOV64rr_ND GR64:$dst, GR64:$src1, GR64:$src2, CC), 0>;
788788
def : InstAlias<"cmov"#Cond#"{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
789789
(CMOV64rm_ND GR64:$dst, GR64:$src1, i64mem:$src2, CC), 0>;
790-
}
791790

791+
def : InstAlias<"setzu"#Cond#"\t$dst", (SETZUCCr GR8:$dst, CC), 0>;
792+
def : InstAlias<"setzu"#Cond#"\t$dst", (SETZUCCm i8mem:$dst, CC), 0>;
793+
def : InstAlias<"set"#Cond#"\t$dst", (SETCCr_EVEX GR8:$dst, CC), 0>;
794+
def : InstAlias<"set"#Cond#"\t$dst", (SETCCm_EVEX i8mem:$dst, CC), 0>;
795+
}
792796
def : InstAlias<"set"#Cond#"\t$dst", (SETCCr GR8:$dst, CC), 0>;
793797
def : InstAlias<"set"#Cond#"\t$dst", (SETCCm i8mem:$dst, CC), 0>;
794798
}

‎llvm/lib/Target/X86/X86InstrCMovSetCC.td

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -127,6 +127,25 @@ let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in {
127127
TB, Sched<[WriteSETCCStore]>;
128128
} // Uses = [EFLAGS]
129129

130+
// SetZUCC and promoted SetCC instructions.
131+
let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1,
132+
hasSideEffects = 0, Predicates = [In64BitMode], Predicates = [HasNDD] in {
133+
def SETZUCCr : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
134+
"setzu${cond}\t$dst", []>,
135+
XD, ZU, NoCD8, Sched<[WriteSETCC]>;
136+
def SETCCr_EVEX : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond),
137+
"set${cond}\t$dst", []>,
138+
XD, PL, Sched<[WriteSETCC]>;
139+
let mayStore = 1 in {
140+
def SETZUCCm : I<0x40, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
141+
"setzu${cond}\t$dst", []>,
142+
XD, ZU, NoCD8, Sched<[WriteSETCCStore]>;
143+
def SETCCm_EVEX : I<0x40, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond),
144+
"set${cond}\t$dst", []>,
145+
XD, PL, Sched<[WriteSETCCStore]>;
146+
}
147+
}
148+
130149
// SALC is an undocumented instruction. Information for this instruction can be found
131150
// here http://www.rcollins.org/secrets/opcodes/SALC.html
132151
// Set AL if carry.

‎llvm/lib/Target/X86/X86InstrControl.td

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -167,24 +167,24 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
167167
}
168168

169169
let Predicates = [Not64BitMode], AsmVariantName = "att" in {
170-
def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
171-
(ins i16imm:$off, i16imm:$seg),
172-
"ljmp{w}\t$seg, $off", []>,
173-
OpSize16, Sched<[WriteJump]>;
174170
def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
175171
(ins i32imm:$off, i16imm:$seg),
176172
"ljmp{l}\t$seg, $off", []>,
177173
OpSize32, Sched<[WriteJump]>;
174+
def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
175+
(ins i16imm:$off, i16imm:$seg),
176+
"ljmp{w}\t$seg, $off", []>,
177+
OpSize16, Sched<[WriteJump]>;
178178
}
179179
let mayLoad = 1 in {
180180
def FARJMP64m : RI<0xFF, MRM5m, (outs), (ins opaquemem:$dst),
181181
"ljmp{q}\t{*}$dst", []>, Sched<[WriteJump]>, Requires<[In64BitMode]>;
182182

183+
def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst),
184+
"{l}jmp{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>;
183185
let AsmVariantName = "att" in
184186
def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst),
185187
"ljmp{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>;
186-
def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst),
187-
"{l}jmp{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>;
188188
}
189189
}
190190

@@ -253,21 +253,21 @@ let isCall = 1 in
253253
}
254254

255255
let Predicates = [Not64BitMode], AsmVariantName = "att" in {
256-
def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
257-
(ins i16imm:$off, i16imm:$seg),
258-
"lcall{w}\t$seg, $off", []>,
259-
OpSize16, Sched<[WriteJump]>;
260256
def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
261257
(ins i32imm:$off, i16imm:$seg),
262258
"lcall{l}\t$seg, $off", []>,
263259
OpSize32, Sched<[WriteJump]>;
260+
def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
261+
(ins i16imm:$off, i16imm:$seg),
262+
"lcall{w}\t$seg, $off", []>,
263+
OpSize16, Sched<[WriteJump]>;
264264
}
265265

266266
let mayLoad = 1 in {
267-
def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
268-
"lcall{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>;
269267
def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
270268
"{l}call{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>;
269+
def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
270+
"lcall{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>;
271271
}
272272
}
273273

‎llvm/test/MC/Disassembler/X86/apx/evex-format.txt

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -215,6 +215,16 @@
215215
# INTEL: sar r17, r16, 123
216216
0x62,0xfc,0xf4,0x10,0xc1,0xf8,0x7b
217217

218+
## MRMXrCC
219+
# ATT: setzuo %r16b
220+
# INTEL: setzuo r16b
221+
0x62,0xfc,0x7f,0x18,0x40,0xc0
222+
223+
## MRMXmCC
224+
# ATT: setzuo (%r16,%r17)
225+
# INTEL: setzuo byte ptr [r16 + r17]
226+
0x62,0xfc,0x7b,0x18,0x40,0x04,0x08
227+
218228
## NoCD8
219229

220230
# ATT: {nf} negq 123(%r16)

‎llvm/test/MC/Disassembler/X86/apx/setcc.txt

Lines changed: 130 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,130 @@
1+
# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
2+
# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
3+
4+
# ATT: {evex} seto %al
5+
# INTEL: {evex} seto al
6+
0x62,0xf4,0x7f,0x08,0x40,0xc0
7+
8+
# ATT: {evex} setno %al
9+
# INTEL: {evex} setno al
10+
0x62,0xf4,0x7f,0x08,0x41,0xc0
11+
12+
# ATT: {evex} setb %al
13+
# INTEL: {evex} setb al
14+
0x62,0xf4,0x7f,0x08,0x42,0xc0
15+
16+
# ATT: {evex} setae %al
17+
# INTEL: {evex} setae al
18+
0x62,0xf4,0x7f,0x08,0x43,0xc0
19+
20+
# ATT: {evex} sete %al
21+
# INTEL: {evex} sete al
22+
0x62,0xf4,0x7f,0x08,0x44,0xc0
23+
24+
# ATT: {evex} setne %al
25+
# INTEL: {evex} setne al
26+
0x62,0xf4,0x7f,0x08,0x45,0xc0
27+
28+
# ATT: {evex} setbe %al
29+
# INTEL: {evex} setbe al
30+
0x62,0xf4,0x7f,0x08,0x46,0xc0
31+
32+
# ATT: {evex} seta %al
33+
# INTEL: {evex} seta al
34+
0x62,0xf4,0x7f,0x08,0x47,0xc0
35+
36+
# ATT: {evex} sets %al
37+
# INTEL: {evex} sets al
38+
0x62,0xf4,0x7f,0x08,0x48,0xc0
39+
40+
# ATT: {evex} setns %al
41+
# INTEL: {evex} setns al
42+
0x62,0xf4,0x7f,0x08,0x49,0xc0
43+
44+
# ATT: {evex} setp %al
45+
# INTEL: {evex} setp al
46+
0x62,0xf4,0x7f,0x08,0x4a,0xc0
47+
48+
# ATT: {evex} setnp %al
49+
# INTEL: {evex} setnp al
50+
0x62,0xf4,0x7f,0x08,0x4b,0xc0
51+
52+
# ATT: {evex} setl %al
53+
# INTEL: {evex} setl al
54+
0x62,0xf4,0x7f,0x08,0x4c,0xc0
55+
56+
# ATT: {evex} setge %al
57+
# INTEL: {evex} setge al
58+
0x62,0xf4,0x7f,0x08,0x4d,0xc0
59+
60+
# ATT: {evex} setle %al
61+
# INTEL: {evex} setle al
62+
0x62,0xf4,0x7f,0x08,0x4e,0xc0
63+
64+
# ATT: {evex} setg %al
65+
# INTEL: {evex} setg al
66+
0x62,0xf4,0x7f,0x08,0x4f,0xc0
67+
68+
# ATT: {evex} seto (%rax)
69+
# INTEL: {evex} seto byte ptr [rax]
70+
0x62,0xf4,0x7f,0x08,0x40,0x00
71+
72+
# ATT: {evex} setno (%rax)
73+
# INTEL: {evex} setno byte ptr [rax]
74+
0x62,0xf4,0x7f,0x08,0x41,0x00
75+
76+
# ATT: {evex} setb (%rax)
77+
# INTEL: {evex} setb byte ptr [rax]
78+
0x62,0xf4,0x7f,0x08,0x42,0x00
79+
80+
# ATT: {evex} setae (%rax)
81+
# INTEL: {evex} setae byte ptr [rax]
82+
0x62,0xf4,0x7f,0x08,0x43,0x00
83+
84+
# ATT: {evex} sete (%rax)
85+
# INTEL: {evex} sete byte ptr [rax]
86+
0x62,0xf4,0x7f,0x08,0x44,0x00
87+
88+
# ATT: {evex} setne (%rax)
89+
# INTEL: {evex} setne byte ptr [rax]
90+
0x62,0xf4,0x7f,0x08,0x45,0x00
91+
92+
# ATT: {evex} setbe (%rax)
93+
# INTEL: {evex} setbe byte ptr [rax]
94+
0x62,0xf4,0x7f,0x08,0x46,0x00
95+
96+
# ATT: {evex} seta (%rax)
97+
# INTEL: {evex} seta byte ptr [rax]
98+
0x62,0xf4,0x7f,0x08,0x47,0x00
99+
100+
# ATT: {evex} sets (%rax)
101+
# INTEL: {evex} sets byte ptr [rax]
102+
0x62,0xf4,0x7f,0x08,0x48,0x00
103+
104+
# ATT: {evex} setns (%rax)
105+
# INTEL: {evex} setns byte ptr [rax]
106+
0x62,0xf4,0x7f,0x08,0x49,0x00
107+
108+
# ATT: {evex} setp (%rax)
109+
# INTEL: {evex} setp byte ptr [rax]
110+
0x62,0xf4,0x7f,0x08,0x4a,0x00
111+
112+
# ATT: {evex} setnp (%rax)
113+
# INTEL: {evex} setnp byte ptr [rax]
114+
0x62,0xf4,0x7f,0x08,0x4b,0x00
115+
116+
# ATT: {evex} setl (%rax)
117+
# INTEL: {evex} setl byte ptr [rax]
118+
0x62,0xf4,0x7f,0x08,0x4c,0x00
119+
120+
# ATT: {evex} setge (%rax)
121+
# INTEL: {evex} setge byte ptr [rax]
122+
0x62,0xf4,0x7f,0x08,0x4d,0x00
123+
124+
# ATT: {evex} setle (%rax)
125+
# INTEL: {evex} setle byte ptr [rax]
126+
0x62,0xf4,0x7f,0x08,0x4e,0x00
127+
128+
# ATT: {evex} setg (%rax)
129+
# INTEL: {evex} setg byte ptr [rax]
130+
0x62,0xf4,0x7f,0x08,0x4f,0x00

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