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‎llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll

Lines changed: 101 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
2+
; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
33

44

55
; Make sure we don't emit a pair of shift for the zext in the preheader. We
@@ -127,3 +127,103 @@ for.body: ; preds = %for.body, %for.body
127127
%niter.ncmp.1 = icmp eq i64 %niter.next.1, %unroll_iter
128128
br i1 %niter.ncmp.1, label %for.cond.cleanup.loopexit.unr-lcssa, label %for.body
129129
}
130+
131+
define i1 @widen_anyof_rdx(ptr %p, i64 %n) {
132+
; CHECK-LABEL: widen_anyof_rdx:
133+
; CHECK: # %bb.0: # %entry
134+
; CHECK-NEXT: li a2, 0
135+
; CHECK-NEXT: vsetvli a3, zero, e64, m4, ta, ma
136+
; CHECK-NEXT: vmclr.m v12
137+
; CHECK-NEXT: vid.v v8
138+
; CHECK-NEXT: .LBB2_1: # %loop
139+
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
140+
; CHECK-NEXT: sub a3, a1, a2
141+
; CHECK-NEXT: slli a4, a2, 2
142+
; CHECK-NEXT: vsetvli a3, a3, e8, mf2, ta, ma
143+
; CHECK-NEXT: add a4, a0, a4
144+
; CHECK-NEXT: vle32.v v14, (a4)
145+
; CHECK-NEXT: vsetvli a4, zero, e32, m2, ta, ma
146+
; CHECK-NEXT: vmsne.vi v13, v14, 0
147+
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
148+
; CHECK-NEXT: vmsltu.vx v14, v8, a3
149+
; CHECK-NEXT: vmand.mm v13, v13, v14
150+
; CHECK-NEXT: add a2, a2, a3
151+
; CHECK-NEXT: vmor.mm v12, v12, v13
152+
; CHECK-NEXT: blt a2, a1, .LBB2_1
153+
; CHECK-NEXT: # %bb.2: # %exit
154+
; CHECK-NEXT: vcpop.m a0, v12
155+
; CHECK-NEXT: snez a0, a0
156+
; CHECK-NEXT: ret
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entry:
158+
br label %loop
159+
loop:
160+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
161+
%phi = phi <vscale x 4 x i1> [ zeroinitializer, %entry ], [ %rec, %loop ]
162+
%avl = sub i64 %n, %iv
163+
%evl = call i32 @llvm.experimental.get.vector.length(i64 %avl, i32 4, i1 true)
164+
165+
%gep = getelementptr i32, ptr %p, i64 %iv
166+
%x = call <vscale x 4 x i32> @llvm.vp.load(ptr %gep, <vscale x 4 x i1> splat (i1 true), i32 %evl)
167+
%cmp = icmp ne <vscale x 4 x i32> %x, zeroinitializer
168+
%rec = call <vscale x 4 x i1> @llvm.vp.merge(<vscale x 4 x i1> %cmp, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i1> %phi, i32 %evl)
169+
170+
%evl.zext = zext i32 %evl to i64
171+
%iv.next = add i64 %iv, %evl.zext
172+
%done = icmp sge i64 %iv.next, %n
173+
br i1 %done, label %exit, label %loop
174+
exit:
175+
%res = call i1 @llvm.vector.reduce.or(<vscale x 4 x i1> %rec)
176+
ret i1 %res
177+
}
178+
179+
180+
define i1 @widen_anyof_rdx_use_in_loop(ptr %p, i64 %n) {
181+
; CHECK-LABEL: widen_anyof_rdx_use_in_loop:
182+
; CHECK: # %bb.0: # %entry
183+
; CHECK-NEXT: li a2, 0
184+
; CHECK-NEXT: vsetvli a3, zero, e64, m4, ta, ma
185+
; CHECK-NEXT: vmclr.m v12
186+
; CHECK-NEXT: vid.v v8
187+
; CHECK-NEXT: .LBB3_1: # %loop
188+
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
189+
; CHECK-NEXT: sub a3, a1, a2
190+
; CHECK-NEXT: slli a4, a2, 2
191+
; CHECK-NEXT: vsetvli a3, a3, e8, mf2, ta, ma
192+
; CHECK-NEXT: add a4, a0, a4
193+
; CHECK-NEXT: vle32.v v14, (a4)
194+
; CHECK-NEXT: vsetvli a5, zero, e32, m2, ta, ma
195+
; CHECK-NEXT: vmsne.vi v13, v14, 0
196+
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
197+
; CHECK-NEXT: vmsltu.vx v14, v8, a3
198+
; CHECK-NEXT: vmand.mm v13, v13, v14
199+
; CHECK-NEXT: vmor.mm v12, v12, v13
200+
; CHECK-NEXT: add a2, a2, a3
201+
; CHECK-NEXT: vsm.v v12, (a4)
202+
; CHECK-NEXT: blt a2, a1, .LBB3_1
203+
; CHECK-NEXT: # %bb.2: # %exit
204+
; CHECK-NEXT: vcpop.m a0, v12
205+
; CHECK-NEXT: snez a0, a0
206+
; CHECK-NEXT: ret
207+
entry:
208+
br label %loop
209+
loop:
210+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
211+
%phi = phi <vscale x 4 x i1> [ zeroinitializer, %entry ], [ %rec, %loop ]
212+
%avl = sub i64 %n, %iv
213+
%evl = call i32 @llvm.experimental.get.vector.length(i64 %avl, i32 4, i1 true)
214+
215+
%gep = getelementptr i32, ptr %p, i64 %iv
216+
%x = call <vscale x 4 x i32> @llvm.vp.load(ptr %gep, <vscale x 4 x i1> splat (i1 true), i32 %evl)
217+
%cmp = icmp ne <vscale x 4 x i32> %x, zeroinitializer
218+
%rec = call <vscale x 4 x i1> @llvm.vp.merge(<vscale x 4 x i1> %cmp, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i1> %phi, i32 %evl)
219+
220+
store <vscale x 4 x i1> %rec, ptr %gep
221+
222+
%evl.zext = zext i32 %evl to i64
223+
%iv.next = add i64 %iv, %evl.zext
224+
%done = icmp sge i64 %iv.next, %n
225+
br i1 %done, label %exit, label %loop
226+
exit:
227+
%res = call i1 @llvm.vector.reduce.or(<vscale x 4 x i1> %rec)
228+
ret i1 %res
229+
}

‎llvm/test/CodeGen/RISCV/riscv-codegenprepare.ll

Lines changed: 90 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -103,3 +103,93 @@ define i64 @bug(i32 %x) {
103103
%b = and i64 %a, 4294967295
104104
ret i64 %b
105105
}
106+
107+
define i1 @widen_anyof_rdx(ptr %p, i64 %n) {
108+
; CHECK-LABEL: @widen_anyof_rdx(
109+
; CHECK-NEXT: entry:
110+
; CHECK-NEXT: br label [[LOOP:%.*]]
111+
; CHECK: loop:
112+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
113+
; CHECK-NEXT: [[PHI:%.*]] = phi <vscale x 4 x i1> [ zeroinitializer, [[ENTRY]] ], [ [[TMP4:%.*]], [[LOOP]] ]
114+
; CHECK-NEXT: [[AVL:%.*]] = sub i64 [[N:%.*]], [[IV]]
115+
; CHECK-NEXT: [[EVL:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
116+
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[IV]]
117+
; CHECK-NEXT: [[X:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr [[GEP]], <vscale x 4 x i1> splat (i1 true), i32 [[EVL]])
118+
; CHECK-NEXT: [[CMP:%.*]] = icmp ne <vscale x 4 x i32> [[X]], zeroinitializer
119+
; CHECK-NEXT: [[TMP4]] = call <vscale x 4 x i1> @llvm.vp.merge.nxv4i1(<vscale x 4 x i1> [[CMP]], <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i1> [[PHI]], i32 [[EVL]])
120+
; CHECK-NEXT: [[EVL_ZEXT:%.*]] = zext i32 [[EVL]] to i64
121+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], [[EVL_ZEXT]]
122+
; CHECK-NEXT: [[DONE:%.*]] = icmp sge i64 [[IV_NEXT]], [[N]]
123+
; CHECK-NEXT: br i1 [[DONE]], label [[EXIT:%.*]], label [[LOOP]]
124+
; CHECK: exit:
125+
; CHECK-NEXT: [[RES:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[TMP4]])
126+
; CHECK-NEXT: ret i1 [[RES]]
127+
;
128+
entry:
129+
br label %loop
130+
loop:
131+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
132+
%phi = phi <vscale x 4 x i1> [ zeroinitializer, %entry ], [ %rec, %loop ]
133+
%avl = sub i64 %n, %iv
134+
%evl = call i32 @llvm.experimental.get.vector.length(i64 %avl, i32 4, i1 true)
135+
136+
%gep = getelementptr i32, ptr %p, i64 %iv
137+
%x = call <vscale x 4 x i32> @llvm.vp.load(ptr %gep, <vscale x 4 x i1> splat (i1 true), i32 %evl)
138+
%cmp = icmp ne <vscale x 4 x i32> %x, zeroinitializer
139+
%rec = call <vscale x 4 x i1> @llvm.vp.merge(<vscale x 4 x i1> %cmp, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i1> %phi, i32 %evl)
140+
141+
%evl.zext = zext i32 %evl to i64
142+
%iv.next = add i64 %iv, %evl.zext
143+
%done = icmp sge i64 %iv.next, %n
144+
br i1 %done, label %exit, label %loop
145+
exit:
146+
%res = call i1 @llvm.vector.reduce.or(<vscale x 4 x i1> %rec)
147+
ret i1 %res
148+
}
149+
150+
151+
define i1 @widen_anyof_rdx_use_in_loop(ptr %p, i64 %n) {
152+
; CHECK-LABEL: @widen_anyof_rdx_use_in_loop(
153+
; CHECK-NEXT: entry:
154+
; CHECK-NEXT: br label [[LOOP:%.*]]
155+
; CHECK: loop:
156+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
157+
; CHECK-NEXT: [[PHI:%.*]] = phi <vscale x 4 x i1> [ zeroinitializer, [[ENTRY]] ], [ [[REC:%.*]], [[LOOP]] ]
158+
; CHECK-NEXT: [[AVL:%.*]] = sub i64 [[N:%.*]], [[IV]]
159+
; CHECK-NEXT: [[EVL:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true)
160+
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[IV]]
161+
; CHECK-NEXT: [[X:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr [[GEP]], <vscale x 4 x i1> splat (i1 true), i32 [[EVL]])
162+
; CHECK-NEXT: [[CMP:%.*]] = icmp ne <vscale x 4 x i32> [[X]], zeroinitializer
163+
; CHECK-NEXT: [[REC]] = call <vscale x 4 x i1> @llvm.vp.merge.nxv4i1(<vscale x 4 x i1> [[CMP]], <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i1> [[PHI]], i32 [[EVL]])
164+
; CHECK-NEXT: store <vscale x 4 x i1> [[REC]], ptr [[GEP]], align 1
165+
; CHECK-NEXT: [[EVL_ZEXT:%.*]] = zext i32 [[EVL]] to i64
166+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], [[EVL_ZEXT]]
167+
; CHECK-NEXT: [[DONE:%.*]] = icmp sge i64 [[IV_NEXT]], [[N]]
168+
; CHECK-NEXT: br i1 [[DONE]], label [[EXIT:%.*]], label [[LOOP]]
169+
; CHECK: exit:
170+
; CHECK-NEXT: [[RES:%.*]] = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> [[REC]])
171+
; CHECK-NEXT: ret i1 [[RES]]
172+
;
173+
entry:
174+
br label %loop
175+
loop:
176+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
177+
%phi = phi <vscale x 4 x i1> [ zeroinitializer, %entry ], [ %rec, %loop ]
178+
%avl = sub i64 %n, %iv
179+
%evl = call i32 @llvm.experimental.get.vector.length(i64 %avl, i32 4, i1 true)
180+
181+
%gep = getelementptr i32, ptr %p, i64 %iv
182+
%x = call <vscale x 4 x i32> @llvm.vp.load(ptr %gep, <vscale x 4 x i1> splat (i1 true), i32 %evl)
183+
%cmp = icmp ne <vscale x 4 x i32> %x, zeroinitializer
184+
%rec = call <vscale x 4 x i1> @llvm.vp.merge(<vscale x 4 x i1> %cmp, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i1> %phi, i32 %evl)
185+
186+
store <vscale x 4 x i1> %rec, ptr %gep
187+
188+
%evl.zext = zext i32 %evl to i64
189+
%iv.next = add i64 %iv, %evl.zext
190+
%done = icmp sge i64 %iv.next, %n
191+
br i1 %done, label %exit, label %loop
192+
exit:
193+
%res = call i1 @llvm.vector.reduce.or(<vscale x 4 x i1> %rec)
194+
ret i1 %res
195+
}

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