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[AArch64][x86] add tests for trunc disguised as vector ops (PR39016); NFC
These correspond to the IR transform from: D52439 llvm-svn: 344353
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‎llvm/test/CodeGen/AArch64/extract-insert.ll

Lines changed: 118 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,118 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64_be-- < %s | FileCheck %s --check-prefix=BE
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; RUN: llc -mtriple=aarch64-- < %s | FileCheck %s --check-prefix=LE
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define i32 @trunc_i64_to_i32_le(i64 %x) {
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; BE-LABEL: trunc_i64_to_i32_le:
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; BE: // %bb.0:
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; BE-NEXT: fmov d0, x0
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; BE-NEXT: rev64 v0.4s, v0.4s
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; BE-NEXT: fmov w0, s0
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; BE-NEXT: ret
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;
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; LE-LABEL: trunc_i64_to_i32_le:
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; LE: // %bb.0:
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; LE-NEXT: fmov d0, x0
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; LE-NEXT: fmov w0, s0
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; LE-NEXT: ret
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%ins = insertelement <2 x i64> undef, i64 %x, i32 0
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%bc = bitcast <2 x i64> %ins to <4 x i32>
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%ext = extractelement <4 x i32> %bc, i32 0
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ret i32 %ext
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}
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define i32 @trunc_i64_to_i32_be(i64 %x) {
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; BE-LABEL: trunc_i64_to_i32_be:
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; BE: // %bb.0:
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; BE-NEXT: fmov d0, x0
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; BE-NEXT: rev64 v0.4s, v0.4s
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; BE-NEXT: mov w0, v0.s[1]
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; BE-NEXT: ret
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;
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; LE-LABEL: trunc_i64_to_i32_be:
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; LE: // %bb.0:
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; LE-NEXT: fmov d0, x0
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; LE-NEXT: mov w0, v0.s[1]
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; LE-NEXT: ret
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%ins = insertelement <2 x i64> undef, i64 %x, i32 0
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%bc = bitcast <2 x i64> %ins to <4 x i32>
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%ext = extractelement <4 x i32> %bc, i32 1
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ret i32 %ext
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}
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define i16 @trunc_i64_to_i16_le(i64 %x) {
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; BE-LABEL: trunc_i64_to_i16_le:
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; BE: // %bb.0:
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; BE-NEXT: fmov d0, x0
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; BE-NEXT: rev64 v0.8h, v0.8h
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; BE-NEXT: umov w0, v0.h[0]
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; BE-NEXT: ret
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;
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; LE-LABEL: trunc_i64_to_i16_le:
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; LE: // %bb.0:
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; LE-NEXT: fmov d0, x0
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; LE-NEXT: umov w0, v0.h[0]
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; LE-NEXT: ret
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%ins = insertelement <2 x i64> undef, i64 %x, i32 0
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%bc = bitcast <2 x i64> %ins to <8 x i16>
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%ext = extractelement <8 x i16> %bc, i32 0
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ret i16 %ext
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}
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define i16 @trunc_i64_to_i16_be(i64 %x) {
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; BE-LABEL: trunc_i64_to_i16_be:
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; BE: // %bb.0:
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; BE-NEXT: fmov d0, x0
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; BE-NEXT: rev64 v0.8h, v0.8h
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; BE-NEXT: umov w0, v0.h[3]
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; BE-NEXT: ret
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;
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; LE-LABEL: trunc_i64_to_i16_be:
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; LE: // %bb.0:
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; LE-NEXT: fmov d0, x0
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; LE-NEXT: umov w0, v0.h[3]
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; LE-NEXT: ret
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%ins = insertelement <2 x i64> undef, i64 %x, i32 0
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%bc = bitcast <2 x i64> %ins to <8 x i16>
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%ext = extractelement <8 x i16> %bc, i32 3
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ret i16 %ext
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}
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define i8 @trunc_i32_to_i8_le(i32 %x) {
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; BE-LABEL: trunc_i32_to_i8_le:
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; BE: // %bb.0:
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; BE-NEXT: fmov s0, w0
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; BE-NEXT: rev32 v0.16b, v0.16b
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; BE-NEXT: umov w0, v0.b[0]
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; BE-NEXT: ret
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;
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; LE-LABEL: trunc_i32_to_i8_le:
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; LE: // %bb.0:
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; LE-NEXT: fmov s0, w0
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; LE-NEXT: umov w0, v0.b[0]
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; LE-NEXT: ret
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%ins = insertelement <4 x i32> undef, i32 %x, i32 0
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%bc = bitcast <4 x i32> %ins to <16 x i8>
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%ext = extractelement <16 x i8> %bc, i32 0
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ret i8 %ext
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}
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define i8 @trunc_i32_to_i8_be(i32 %x) {
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; BE-LABEL: trunc_i32_to_i8_be:
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; BE: // %bb.0:
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; BE-NEXT: fmov s0, w0
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; BE-NEXT: rev32 v0.16b, v0.16b
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; BE-NEXT: umov w0, v0.b[3]
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; BE-NEXT: ret
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;
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; LE-LABEL: trunc_i32_to_i8_be:
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; LE: // %bb.0:
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; LE-NEXT: fmov s0, w0
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; LE-NEXT: umov w0, v0.b[3]
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; LE-NEXT: ret
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%ins = insertelement <4 x i32> undef, i32 %x, i32 0
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%bc = bitcast <4 x i32> %ins to <16 x i8>
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%ext = extractelement <16 x i8> %bc, i32 3
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ret i8 %ext
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}
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‎llvm/test/CodeGen/X86/extract-insert.ll

Lines changed: 54 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ define i8 @extractelt_bitcast(i32 %x) nounwind {
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}
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; TODO: This should have folded to avoid vector ops, but the transform
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; is guarded by 'hasOneUse'. That limitation apparently makes some AMDGPU
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; is guarded by 'hasOneUse'. That limitation apparently makes some AMDGPU
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; codegen better.
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define i8 @extractelt_bitcast_extra_use(i32 %x, <4 x i8>* %p) nounwind {
@@ -60,3 +60,56 @@ define i8 @extractelt_bitcast_extra_use(i32 %x, <4 x i8>* %p) nounwind {
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ret i8 %ext
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}
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define i32 @trunc_i64_to_i32_le(i64 %x) {
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; X86-LABEL: trunc_i64_to_i32_le:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: trunc_i64_to_i32_le:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %xmm0
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; X64-NEXT: movd %xmm0, %eax
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; X64-NEXT: retq
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%ins = insertelement <2 x i64> undef, i64 %x, i32 0
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%bc = bitcast <2 x i64> %ins to <4 x i32>
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%ext = extractelement <4 x i32> %bc, i32 0
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ret i32 %ext
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}
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define i16 @trunc_i64_to_i16_le(i64 %x) {
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; X86-LABEL: trunc_i64_to_i16_le:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: # kill: def $ax killed $ax killed $eax
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; X86-NEXT: retl
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;
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; X64-LABEL: trunc_i64_to_i16_le:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %xmm0
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; X64-NEXT: movd %xmm0, %eax
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; X64-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-NEXT: retq
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%ins = insertelement <2 x i64> undef, i64 %x, i32 0
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%bc = bitcast <2 x i64> %ins to <8 x i16>
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%ext = extractelement <8 x i16> %bc, i32 0
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ret i16 %ext
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}
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define i8 @trunc_i32_to_i8_le(i32 %x) {
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; X86-LABEL: trunc_i32_to_i8_le:
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; X86: # %bb.0:
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; X86-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-NEXT: retl
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;
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; X64-LABEL: trunc_i32_to_i8_le:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: # kill: def $al killed $al killed $eax
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; X64-NEXT: retq
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%ins = insertelement <4 x i32> undef, i32 %x, i32 0
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%bc = bitcast <4 x i32> %ins to <16 x i8>
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%ext = extractelement <16 x i8> %bc, i32 0
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ret i8 %ext
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}
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